Preliminary Datasheet

LP6288

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LP6288

Version 0.1 JAN.-2018

Application Information (Continued)

4. IIC REGISTER MAP

The lowest bit number (0) represents the least bit, the highest bit number (7) represents the most bit, and R/W

indicates whether the bit is read only (R), write only (W), or both read and write (R/W).

Block

Parameter

Symbol

Address

Range

Resolution

EEPROM

Factory Value

BIT(Step)

Channel

Disable Channel Output

Dis_CH

00H

00H

-

3FH

--

00H

6bits

Boost

Boost Output Voltage

BST_O

01H

00H

-

3FH

(13.5V

-

19.8V)

0.1V

21H

(16.8V)

6bits

(64 Steps)

HVS Voltage

BST_HVS

02H

00H

-

0FH

(0V

-

3V)

0.2V

08H

(1.6V)

4bits

(16 Steps)

Current Limit

BST_ILIM

03H

00H

-

07H

(0A

-

2.8A)

0.4A

04H

(1.6A)

3bits

(8 Steps)

Soft Start Time

BST_SST

04H

00H

-

01H

(10ms

-

20ms)

10ms

00H

(10ms)

1bit

(2 Steps)

Buck

Buck1 Output Voltage

BKO1

05H

00H

-

0FH

(2.2V

-

3.7V)

0.1V

0BH

(3.3V)

4bits

(16 Steps)

Buck2 Output Voltage

BKO2

06H

00H

-

19H

(0.8V

-

3.3V)

0.1V

04H

(1.2V)

5bits

(32 Steps)

Buck3 Output Voltage

BKO3

07H

00H

-

3FH

(4.8V

-

11.1V)

0.1V

21H

(8.1V)

6bits

(64 Steps)

VGH

VGH Output Voltage

VGH_L

08H

00H

-

0FH

(20V

-

35V)

1V

08H

(28V)

4bits

(16 Steps)

VGH Output Offset

VGH_H

09H

00H

-

0FH

(0V

-

15V)

1V

08H

(8V)

4bits

(16 Steps)

GPM Stop Level

VGPM

0AH

00H

-

03H

(0V

-

15V)

5V

03H

(15V)

2bits

(4 Steps)

VGL

VGL Output Voltage

VGL

0BH

00H

-

0FH

(-5.5V

-

-14.5V)

0.6V

08H

(-10.3V)

4bits

(16 Steps)

Sel_Gate

Select Gate Function

Gate

20H

00H - 01H

--

00H

(Disable)

1bit

Memory

Write Remain Time

MRT

FEH

0FH(Fixed)

--

0FH

4bits

Control

Control Register

Ctrl_Reg

FFH

00H-81H

--

00H

8bits

Set Channel Output (Register Address – 00H)

Disable Channel Output

Addr: 00H

Default Value : Dis_ CH (Register)=0x00H, All Channel Enable.

D7

D6

D5

D4

D3

D2

D1

D0

R

R

R/W

R/W

R/W

R/W

R/W

R/W

0

0

BK2

BK3

VGH

VGL

VGHM

NTC

Disable Channel Output

Register

Bit Description

0

Enable Channel Output

1

Disable Channel Output