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AS7C1024B 数据表(PDF) 5 Page - Alliance Semiconductor Corporation

部件名 AS7C1024B
功能描述  5V 128K X 8 CMOS SRAM
PDF  9 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  ALSC [Alliance Semiconductor Corporation]
网页  https://www.alliancememory.com
标志 ALSC - Alliance Semiconductor Corporation

AS7C1024B 数据表(HTML) 5 Page - Alliance Semiconductor Corporation

  AS7C1024B Datasheet HTML 1Page - Alliance Semiconductor Corporation AS7C1024B Datasheet HTML 2Page - Alliance Semiconductor Corporation AS7C1024B Datasheet HTML 3Page - Alliance Semiconductor Corporation AS7C1024B Datasheet HTML 4Page - Alliance Semiconductor Corporation AS7C1024B Datasheet HTML 5Page - Alliance Semiconductor Corporation AS7C1024B Datasheet HTML 6Page - Alliance Semiconductor Corporation AS7C1024B Datasheet HTML 7Page - Alliance Semiconductor Corporation AS7C1024B Datasheet HTML 8Page - Alliance Semiconductor Corporation AS7C1024B Datasheet HTML 9Page - Alliance Semiconductor Corporation  
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AS7C1024B
3/26/04, v 1.2
Alliance Semiconductor
P. 5 of 9
®
Write waveform 1 (WE controlled)10,11,12
Write cycle (over the operating range)11, 12
Parameter
Symbol
-10
-12
-15
-20
Unit
Notes
Min Max Min
Max
Min
Max
Min
Max
Write cycle time
tWC
10
-
12
–
15
–
20
–
ns
Chip enable (CE1) to write end
tCW1
8
-
9
–
10
–
12
–
ns
12
Chip enable (CE2) to write end
tCW2
8
-
9
–
10
–
12
–
ns
12
Address setup to write end
tAW
8
-
9
–
10
–
12
–
ns
Address setup time
tAS
00
–
0
–
0
–
ns
12
Write pulse width
tWP
78
–
9
–
12
–
ns
Write recovery time
tWR
0-0
–
0
–
0
–
ns
Address hold from end of write
tAH
0-0
–
0
–
0
–
ns
Data valid to write end
tDW
56
–
8
–
10
–
ns
Data hold time
tDH
00
–
0
–
0
–
ns
4, 5
Write enable to output in high Z
tWZ
-
5
–
6
–
7
–
8
ns
4, 5
Output active from write end
tOW
1
-
1
–
1
–
2
–
ns
4, 5
tAW
tAH
tWC
Address
WE
DOUT
tDH
tOW
tDW
tWZ
tWP
tAS
Data valid
DIN
tWR



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