AS7C1024B

3/26/04, v 1.2

Alliance Semiconductor

P. 6 of 9

®

AC test conditions

Notes

1

2

This parameter is sampled and not 100% tested.

3

For test conditions, see AC Test Conditions, Figures A and B.

5

This parameter is guaranteed, but not 100% tested.

6WE is high for read cycle.

7CE1 and OE are low and CE2 is high for read cycle.

8

Address valid prior to or coincident with CE1 transition Low.

9

All read cycle timings are referenced from the last valid address to the first transitioning address.

10 N/A

11

All write cycle timings are referenced from the last valid address to the first transitioning address.

12 CE1 and CE2 have identical timing.

13 C = 30 pF, except all high Z and low Z parameters where C = 5 pF.

Address

CE1

WE

CE2

Data valid

– Output load: see Figure B.

– Input pulse level: GND to 3.5V. See Figure A.

– Input rise and fall times: 2 ns. See Figure A.

– Input and output timing reference levels: 1.5V.

168

Ω

Thevenin equivalent:

+1.728V

255

Ω

480

Ω

GND

+5V

Figure B: 5V Output load

10%

90%

10%

90%

GND

+3.5V

Figure A: Input pulse

2 ns