INMP441

I²S DATA INTERFACE

The slave serial-data port’s format is I²S, 24-bit, twos complement. There must be 64 SCK cycles in each WS stereo frame, or 32 SCK

cycles per data-word. The L/R control pin determines whether the INMP441 outputs data in the left or right channel. For a stereo

application, the SD pins of the left and right INMP441 microphones should be tied together as shown in Figure 7. The format of a

stereo I²S data stream is shown in Figure 8. Figures 9 and 10 show the formats of a mono microphone data stream for left and right

microphones, respectively.

Data Output Mode

The output data pin (SD) is tri-stated when it is not actively driving I²S output data. SD immediately tri-states after the LSB is output

so that another microphone can drive the common data line.

The SD trace should have a pull-down resistor to discharge the line during the time that all microphones on the bus have tri-stated

their outputs. A 100 kΩ resistor is sufficient for this, as shown in Figure 7.

Data Word Length

Data-Word Format

The default data format is I²S (two’s complement), MSB-first. In this format, the MSB of each word is delayed by one SCK cycle from

the start of each half-frame.

Figure 7. System Block Diagram

SYSTEM MASTER

(DSP, MICROCONTROLLER,

CODEC)

CHIPEN

SCK

WS

L/R

SD

VDD

LEFT

INMP441

GND GND GND

0.1µF

FROM VOLTAGE

REGULATOR

(1.8V TO 3.3V)

CHIPEN

SCK

WS

L/R

SD

VDD

RIGHT

INMP441

GND GND GND

0.1µF

100kΩ

Page 11 of 21

Document Number: DS-INMP441-00

Revision: 1.1