IS25LP256D-RJLA3 datasheet(119/174 Pages) ISSI

部件名	IS25LP256D-RJLA3

功能描述	SERIAL FLASH MEMORY WITH 166/133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE

PDF	174 Pages

Scroll/Zoom	100%

制造商	ISSI [Integrated Silicon Solution, Inc]

网页	http://www.issi.com

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119 / 174 page

IS25LP256D

IS25WP256D

Integrated Silicon Solution, Inc.- www.issi.com

119

Rev A6

04/15/2019

Figure 8.86 FRDDTR Sequence (BDh [EXTADD=0], 3-byte address)

CE #

SCK

IO0

IO1

Instruction = BDh

CE #

SCK

IO0

IO1

3-byte Address

High Impedance

...

Mode 3

Mode 0

...

22 20 18

7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1

4 Dummy Cycles

23 21 19

Data Out

...

6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0

Data Out

16 14 12

17 15 13

7 5

6 4

3 1

2 0

Mode Bits

...

Mode Bits

...

Notes:

If the mode bits=AXh (where X is don’t care), it can execute the AX read mode (without command). When the mode

bits are different from AXh, the device exits the AX read operation.

2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.

3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bits cycles

are same, then X should be Hi-Z.

IS25LP256D-RJLA3 数据表(PDF) 119 Page - Integrated Silicon Solution, Inc

IS25LP256D-RJLA3 数据表(HTML) 119 Page - Integrated Silicon Solution, Inc

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