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IS25LP256D-RGLA3 数据表(PDF) 166 Page - Integrated Silicon Solution, Inc |
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IS25LP256D-RGLA3 数据表(HTML) 166 Page - Integrated Silicon Solution, Inc |
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166 / 174 page ![]() IS25LP256D IS25WP256D Integrated Silicon Solution, Inc.- www.issi.com 166 Rev A6 04/15/2019 9.8 POWER-UP AND POWER-DOWN At Power-up and Power-down, the device must be NOT SELECTED until Vcc reaches at the right level. (Adding a simple pull-up resistor on CE# is recommended.) Power up timing VCC VCC(max) VCC(min) V(write inhibit) Reset State tVCE tPUW Read Access Allowed Device fully accessible Chip Selection Not Allowed All Write Commands are Rejected Symbol Parameter Min. Max Unit tVCE(1) Vcc(min) to CE# Low 1 ms tPUW(1) Power-up time delay to write instruction 1 10 ms VWI(1) Write Inhibit Voltage IS25LP 2.1 V IS25WP 1.4 Note: These parameters are characterized and not 100% tested. |
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