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IS25LP256D-RGLA3 数据表(PDF) 57 Page - Integrated Silicon Solution, Inc

部件名 IS25LP256D-RGLA3
功能描述  SERIAL FLASH MEMORY WITH 166/133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE
PDF  174 Pages
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制造商  ISSI [Integrated Silicon Solution, Inc]
网页  http://www.issi.com
标志 ISSI - Integrated Silicon Solution, Inc

IS25LP256D-RGLA3 数据表(HTML) 57 Page - Integrated Silicon Solution, Inc

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IS25LP256D
IS25WP256D
Integrated Silicon Solution, Inc.- www.issi.com
57
Rev A6
04/15/2019
Figure 8.7 Fast Read Dual I/O Sequence (BBh [EXTADD=0], 3-byte address)
7
5
3
7
5
1
3
1
Data Out 1
Instruction = BBh
22
CE #
SCK
2
0
6
4
3-byte Address
High Impedance
20
18
...
0
1
2
3
4
5
6
7
8
9
10
...
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
Mode 3
Mode 0
...
tV
23
3
1
7
5
21
19
...
IO0
IO1
3
1
2
0
6
4
2
6
4
0
2
0
4 Dummy Cycles
7
5
3
1
6
4
2
0
7
5
...
6
4
...
CE #
SCK
IO0
IO1
Data Out 2
Data Out 3
Mode Bits
Mode Bits
Notes:
1.
If the mode bits=AXh (where X is don’t care), it can execute the AX read mode (without command). When the mode
bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.
3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bits cycles
are same, then X should be Hi-Z.



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