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IS25LP032D-RHLA3 数据表(PDF) 20 Page - Integrated Silicon Solution, Inc

部件名 IS25LP032D-RHLA3
功能描述  SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE
PDF  118 Pages
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制造商  ISSI [Integrated Silicon Solution, Inc]
网页  http://www.issi.com
标志 ISSI - Integrated Silicon Solution, Inc

IS25LP032D-RHLA3 数据表(HTML) 20 Page - Integrated Silicon Solution, Inc

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IS25LP032D
IS25WP032D
Integrated Silicon Solution, Inc.- www.issi.com
20
Rev. A12
08/04/2020
6. REGISTERS
The device has various sets of Registers: Status, Function, Read, Extended Read and Autoboot.
When the register is read continuously, the same data is output repeatedly until CE# goes HIGH.
6.1 STATUS REGISTER
Status Register Format and Status Register Bit Definitions are described in Table 6.1 & Table 6.2.
Table 6.1 Status Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SRWD
QE
BP3
BP2
BP1
BP0
WEL
WIP
Default
0
0
0
0
0
0
0
0
Table 6.2 Status Register Bit Definition
Bit
Name
Definition
Read-
/Write
Type
Bit 0
WIP
Write In Progress Bit:
"0" indicates the device is ready(default)
"1" indicates a write cycle is in progress and the device is busy
R
Volatile
Bit 1
WEL
Write Enable Latch:
"0" indicates the device is not write enabled (default)
"1" indicates the device is write enabled
R/W1
Volatile
Bit 2
BP0
Block Protection Bit: (See Table 6.4 for details)
"0" indicates the specific blocks are not write-protected (default)
"1" indicates the specific blocks are write-protected
R/W
Non-Volatile
Bit 3
BP1
Bit 4
BP2
Bit 5
BP3
Bit 6
QE
Quad Enable bit:
“0” indicates the Quad output function disable (default)
“1” indicates the Quad output function enable
R/W
Non-Volatile
Bit 7
SRWD
Status Register Write Disable: (See Table 7.1 for details)
"0" indicates the Status Register is not write-protected (default)
"1" indicates the Status Register is write-protected
R/W
Non-Volatile
Note1: WEL bit can be written by WREN and WRDI commands, but cannot by WRSR command.
The BP0, BP1, BP2, BP3, QE, and SRWD are non-volatile memory cells that can be written by a Write Status
Register (WRSR) instruction. The default value of the BP0, BP1, BP2, BP3, QE,
and SRWD bits were set to “0” at
factory. The Status Register can be read by the Read Status Register (RDSR).
The function of Status Register bits are described as follows:
WIP bit: Write In Progress (WIP) is read-only, and can be used to detect the progress or completion of a Program,
Erase, or Write/Set Non-Volatile/OTP Register operation.
WIP is set to “1” (busy state) when the device is executing
the operation. During this time the device will ignore further instructions except for Read Status/Function/Extended
Read Register and Software/Hardware Reset instructions. In addition to the instructions, an Erase/Program
Suspend instruction also can be executed during a Program or an Erase operation. When an operation has
completed, WIP is cleared to “0” (ready state) whether the operation is successful or not and the device is ready
for further instructions.
WEL bit: Write Enable Latch (WEL) indicates the status of the internal write
enable latch. When WEL is “0”, the
internal write enable latch is disabled and the write operations described in Table 6.3 are inhibited. When WEL is
“1”, the Write operations are allowed. WEL bit is set by a Write Enable (WREN) instruction. Each Write Non-Volatile
Register, Program and Erase instruction must be preceded by a WREN instruction. The volatile register related
commands such as the Set Volatile Read Register and the Set Volatile Extended Read Register don’t require to



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