IS25LP032D-RHLA3 datasheet(52/118 Pages) ISSI

52 / 118 page

IS25LP032D

IS25WP032D

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A12

08/04/2020

8.11 SECTOR ERASE OPERATION (SER, D7h/20h)

A Sector Erase (SER) instruction erases a 4 Kbyte sector before the execution of a SER instruction, the Write

Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL bit is automatically reset after

the completion of Sector Erase operation.

A SER instruction is entered, after CE# is pulled low to select the device and stays low during the entire instruction

sequence The SER instruction code, and three address bytes are input via SI. Erase operation will start immediately

after CE# is pulled high. The internal control logic automatically handles the erase voltage and timing.

The progress or completion of the erase operation can be determined by reading the WIP bit in the Status Register

using a RDSR instruction.

If the WIP bit is “1”, the erase operation is still in progress. If the WIP bit is “0”, the erase operation has been

completed.

Figure 8.14 Sector Erase Sequence in SPI mode

Instruction = D7h/20h

CE #

SCK

3-byte Address

High Impedance

...

Mode 3

Mode 0

Figure 8.15 Sector Erase Sequence In QPI Mode

D7h/20h

CE#

SCK

IO[3:0]

3-byte Address

Mode 3

Mode 0

23:20 19:16 15:12 11:8

7:4

3:0

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