ADC32RF83 datasheet(55/138 Pages) TI

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Test Patterns

Transport Layer

Scrambler

1+x

14+x15

Comma Characters

Initial Lane

Alignment

Link Layer

JESD204B Block

D[3:0]

SYNCB

Frame Data

Mapping

8b, 10b

Encoding

JESD

204B

INA

Sample Clock

SysRef

JESD204B

D[3:0]

SYNCB

JESD

204B

INB

JESD204B

D[3:0]

ADC32RF80, ADC32RF83

www.ti.com

SBAS774A – MAY 2016 – REVISED DECEMBER 2016

Product Folder Links: ADC32RF80 ADC32RF83

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8.4 Device Functional Modes

8.4.1 Device Configuration

The ADC32RF8x can be configured using a serial programming interface, as described in the Serial Interface

section. In addition, the device has one dedicated parallel pin (PDN) for controlling the power-down modes.

8.4.2 JESD204B Interface

The ADC32RF8x supports device subclass 1 with a maximum output data rate of 12.5 Gbps for each serial

transmitter.

An external SYSREF signal is used to align all internal clock phases and the local multiframe clock to a specific

sampling clock edge. This alignment allows synchronization of multiple devices in a system and minimizes timing

and alignment uncertainty. The SYNCB input is used to control the JESD204B SerDes blocks, as shown in

Figure 132.

Depending on the ADC sampling rate, the JESD204B output interface can be operated with one, two, or four

lanes per ADC channel. The JESD204B setup and configuration of the frame assembly parameters is controlled

through the SPI interface.

Figure 132. JESD Signal Overview

The JESD204B transmitter block consists of the transport layer, the data scrambler, and the link layer, as shown

in Figure 133. The transport layer maps the ADC output data into the selected JESD204B frame data format and

manages if the ADC output data or test patterns are transmitted. The link layer performs the 8b, 10b data

encoding as well as the synchronization and initial lane alignment using the SYNC input signal. Optionally, data

from the transport layer can be scrambled.

Figure 133. JESD Digital Block Implementation

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