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ADC32RF83 数据表(PDF) 120 Page - Texas Instruments |
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ADC32RF83 数据表(HTML) 120 Page - Texas Instruments |
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120 / 138 page ![]() Power Supplies RESET SEN t1 t2 t3 120 ADC32RF80, ADC32RF83 SBAS774A – MAY 2016 – REVISED DECEMBER 2016 www.ti.com Product Folder Links: ADC32RF80 ADC32RF83 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated 9.1.2 Hardware Reset Timing information for the hardware reset is shown in Figure 253 and Table 118. Figure 253. Hardware Reset Timing Diagram Table 118. Hardware Reset Timing Information MIN TYP MAX UNIT t1 Power-on delay from power-up to active high RESET pulse 1 ms t2 Reset pulse duration: active high RESET pulse duration 1 µs t3 Register write delay from RESET disable to SEN active 100 ns |
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