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数据搜索系统，热门电子元器件搜索 |
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STM32F722IC 数据表(PDF) 21 Page - STMicroelectronics |
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STM32F722IC 数据表(HTML) 21 Page - STMicroelectronics |
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21 / 229 page  DS11853 Rev 6 21/229 STM32F722xx STM32F723xx Description 49 Figure 6. STM32F722xx and STM32F723xx block diagram 1. The timers connected to APB2 are clocked from TIMxCLK up to 216 MHz, while the timers connected to APB1 are clocked from TIMxCLK either up to 108 MHz or 216 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register. 2. Available only on the STM32F723xx devices. 3. Available only on the STM32F723xx LQFP100 package. MSv41012V4 GPIO PORT A AHB/APB2 EXT IT. WKUP 168 AF PA[15:0] TIM1 / PWM 4 compl. chan. (TIM1_CH1[1:4]N), 4 chan. (TIM1_CH1[1:4]ETR, BKIN as AF USART1 RX, TX, SCK, CTS, RTS as AF SPI1/I2S1 8 analog inputs common to the 3 ADCs VDDREF_ADC UART4 MOSI, MISO, SCK NSS as AF SPI3/I2S3 DAC1 as AF ITF WWDG 4 KB BKPRAM OSC32_IN OSC32_OUT VDDA, VSSA NRESET smcard irDA 16b SDMMC1 D[7:0] CMD, CK as AF VBAT = 1.8 to 3.6 V GPDMA2 SCL, SDA, SMBAL as AF I2C3/SMBUS GP-DMA2 8 Streams FIFO ACCEL/ CACHE SRAM1 176KB CLK, NE [3:0], A[23:0], D[31:0], NOEN, NWEN, NBL[3:0], SDCLKE[1:0] SDNE[1:0], SDNWE, NL NWAIT, INTN DP DM SCL, SDA, INT, ID, VBUS AHB1 216 MHz US AR T 2 M B p s Temperature sensor ADC1 ADC2 ADC3 IF IF POR/PDR BOR SUPPLY SUPERVISION PVD Int POR reset XTAL 32 kHz MGT RTC RC HS RC LS Standby interface @VDDA AWU RCC Reset & control PLL1+PLL2+PLL3 VDDUSB33 = 3.0 to 3.6 V VSS VCAP1 VOLT. REG 3.3V TO 1.2V VDD12 BBgen + POWER MNGT Backup register TIM14 TIM9 2 channels as AF DAC1 TIM6 TIM7 TIM2 TIM3 TIM4 TIM5 TIM12 SRAM2 16KB AHB2 216 MHz GP-DMA1 8 Streams FIFO PB[15:0] PC[15:0] PD[15:0] PE[15:0] PF[15:0] PG[15:0] PH[15:0] PI[11:0] GPIO PORT B GPIO PORT C GPIO PORT D GPIO PORT E GPIO PORT F GPIO PORT G GPIO PORT H GPIO PORT I TIM8 / PWM 16b 16b TIM10 16b TIM11 16b smcard irDA USART6 4 compl. chan.(TIM8_CH1[1:4]N), 4 chan. (TIM8_CH1[1:4], ETR, BKIN as AF 1 channel as AF 1 channel as AF RX, TX, SCK, CTS, RTS as AF 8 analog inputs common to the ADC1 & 2 8 analog inputs for ADC3 DAC2 as AF 16b 16b bxCAN1 I2C2/SMBUS I2C1/SMBUS SCL, SDA, SMBAL as AF SCL, SDA, SMBAL as AF SPI2/I2S2 MOSI, MISO, SCK NSS as AF TX, RX RX, TX as AF RX, TX as AF RX, TX, SCK CTS, RTS as AF RX, TX, SCK CTS, RTS as AF 1 channel as AF UART5 USART3 USART2 smcard irDA smcard irDA 16b 16b 16b 1 channel as AF TIM13 2 channels as AF 32b 16b 16b 32b 4 channels 4 channels, ETR as AF 4 channels, ETR as AF 4 channels, ETR as AF GPDMA1 AHB/ APB1 OSC_IN OSC_OUT XTAL OSC 4- 16MHz SPI4 SCK, NSS as AF SPI5 SCK, NSS as AF MOSI, MISO, MOSI, MISO, RX, TX as AF UART7 RX, TX as AF UART8 SAI1 SD, SCK, FS, MCLK as AF NRAS, NCAS, NADV RTC_TS RTC_TAMPx RTC_OUT Arm CPU Cortex-M7 AXIM AHBP AHBS DTCM ICTM TRACECK TRACED[3:0] JTRST, JTDI, JTCK/SWCLK JTDO/SWD, JTDO JTAG & SW NVIC ETM MPU FPU DTCM RAM 64KB ITCM RAM 16KB Quad-SPI CLK, CS,D[7:0] VDDMMC33 = 3.0 to 3.6V WKUP[4:0] LPTIM1 16b SAI2 SD, SCK, FS, MCLK as AF EXT MEM CTL (FMC) SRAM, SDRAM, NOR-Flash, NAND-Flash, SDRAM 216MHz I-Cache 8KB D-Cache 8KB @VDDA @VDD33 @VDD33 @VSW @VDDA @VDDA FLASH 512KB SDMMC2 D[7:0] CMD, CK as AF DAC2 SYSCFG WDG32K VDD = 1.8 to 3.6 V CRC SCK, NSS as AF MOSI, MISO, RNG USB HS PHY PLL LDO USB OTG FS SCL, SDA, INT, ID, VBUS OTG HS PHY CONTROLLER (2) DP, DM ULPI:CK, D[7:0], DIR, STP, NXT SCL/SDA, INT, ID, VBUS USB OTG HS PLL1 LDO DMA/ FIFO PLL2 (2) ULPI:CK, D[7:0], DIR, STP, NXT BGR VDDPHYHS = 3.0 to 3.6V (3) |
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