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STSPIN820 数据表(PDF) 11 Page - STMicroelectronics |
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STSPIN820 数据表(HTML) 11 Page - STMicroelectronics |
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11 / 29 page ![]() DocID031065 Rev 2 11/29 STSPIN820 Pin connection 29 12 OUTB1 Power output Power bridge output side B1 13 SENSEB2 Power output Sense output of the bridge B 14 SENSEB1 Power output Sense output of the bridge B 15 SNSB Analog input Full-bridge B current regulator sense input 16 STBY\RESET Logic input Standby\reset input. When forced low the device enters in low consumption mode. 17 EN\FAULT Logic input\ open-drain output Logic input 5 V compliant with open-drain output. This is the power stage enable (when low, the power stage is turned off) and is forced low through the integrated open-drain MOSFET when a failure occurs. 18 DECAY Logic input Decay mode selection input. High logic level sets slow decay mode; low logic level sets mixed decay mode (see Section 5.3 on page 16 for more details). 19 STCK Logic input Step clock input 20 DIR Logic input Direction input 21 MODE1 Logic input Step mode selection input 1 22 MODE2 Logic input Step mode selection input 2 23 MODE3 Logic input Step mode selection input 3 24 TOFF Analog input Internal oscillator frequency adjustment Table 6. Pin description (continued) No. Name Type Function |
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