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IIS3DHHC 数据表(PDF) 12 Page - STMicroelectronics |
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IIS3DHHC 数据表(HTML) 12 Page - STMicroelectronics |
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12 / 30 page ![]() 5.2 FIFO mode In FIFO mode (FIFO_CTRL (2Eh) (FMODE [2:0] = 001) data from the output channels are stored in the FIFO memory until it is full, when 32 unread samples are stored in memory, data collecting is stopped. To reset FIFO content, Bypass mode should be selected by writing FIFO_CTRL (2Eh) (FMODE [2:0]) to '000'. After this reset command, it is possible to restart FIFO mode, writing FIFO_CTRL (2Eh) (FMODE [2:0]) to '001'. A FIFO threshold interrupt can be enabled (INT1_OVR bit in INT1_CTRL (21h) or INT2_OVR bit in INT2_CTRL (22h)) in order to be raised when the FIFO is filled to the level specified by the FTH[4:0] bits of FIFO_CTRL (2Eh). Figure 10. FIFO mode x0 y z0 y0 x1 y1 z1 x2 y2 z2 x31 y31 z31 xi,yi,zi IIS3DHHC FIFO mode DS12292 - Rev 3 page 12/30 |
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