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FS32K142MHTXMLLTR 数据表(PDF) 55 Page - NXP Semiconductors |
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FS32K142MHTXMLLTR 数据表(HTML) 55 Page - NXP Semiconductors |
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55 / 100 page  Table 40. 12-bit ADC operating conditions Symbol Description Conditions Min. Typ.1 Max. Unit Notes S32K1xx/ S32K14xW S32K1xx/ S32K14xW S32K1xx S32K14xW VREFH ADC reference voltage high See Voltage and current operating requirements for values VDDA See Voltage and current operating requirements for values V 2 VREFL ADC reference voltage low See Voltage and current operating requirements for values 0 See Voltage and current operating requirements for values mV 2 VADIN Input voltage VREFL — VREFH V RS Source impedendance fADCK < 4 MHz — — 5 kΩ RSW1 Channel Selection Switch Impedance — 0.75 1.2 kΩ RAD Sampling Switch Impedance — 2 5 kΩ CP1 Pin Capacitance — 10 — pF CP2 Analog Bus Capacitance — — 4 pF CS Sampling capacitance — 4 5 pF fADCK ADC conversion clock frequency Normal usage 2 40 50 40 MHz 3, 4 fCONV ADC conversion frequency No ADC hardware averaging.5 Continuous conversions enabled, subsequent conversion time 46.4 928 1160 Ksps 6, 7 ADC hardware averaging set to 32. 5 Continuous conversions enabled, subsequent conversion time 1.45 29 36.25 Ksps 6, 7 1. Typical values assume VDDA = 5 V, Temp = 25 °C, fADCK = 40 MHz, RAS=20 Ω, and CAS=10 nF unless otherwise stated. Typical values are for reference only, and are not tested in production. 2. For packages without dedicated VREFH and VREFL pins, VREFH is internally tied to VDDA, and VREFL is internally tied to VSS. To get maximum performance, reference supply quality should be better than SAR ADC. See application note AN5032 for details. 3. Clock and compare cycle need to be set according to the guidelines mentioned in the Reference Manual . 4. ADC conversion will become less reliable above maximum frequency. 5. When using ADC hardware averaging, see the Reference Manual to determine the most appropriate setting for AVGS. |
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