ADAR2004 datasheet(17/37 Pages) AD

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Data Sheet

ADAR2004

Rev. 0 | Page 17 of 37

RECEIVERS

There are four independent receive channels, each with fully

differential inputs and outputs. Each channel includes an RF

LNA front end, a downconverting mixer, and a dedicated IF

VGA. The inputs operate from 10 GHz to 40 GHz and are

intended to be connected to dipole antennas, whereas the outputs

operate from low frequency to 800 MHz and are meant to be

directly connected to an ADC. The bias levels of the LNAs, mixers,

and IF VGAs are adjustable through the SPI. There is one setting

for all the LNAs (LNA_BIAS in Register 0x015), one setting for

the mixers (MIX_BIAS in Register 0x015), and one setting for

the IF VGAs (IFAMP_BIAS in Register 0x016). The IF VGAs

also have a setting for VOCM (IFAMP_CM in Register 0x017).

See the Bias Points and Voltages section for more information.

Although normal operation envisages all four receive channels

operating at one time, the programmability allows any

combination of receive channels to be turned on or off

simultaneously.

TEMPERATURE SENSOR

The ADAR2004 has an on-chip temperature sensor that feeds

into a dedicated 8-bit ADC for monitoring the temperature of

the chip. Use the following equation to calculate the approximate

temperature in Celsius from the ADC output:

TA = (1.05 × ADC_OUTPUT) – 80

where ADC_OUTPUT is the ADC output word in Register 0x031.

ADC AND ADC CLOCK

The ADAR2004 has an on-chip, 8-bit ADC and a variable clock

input, each with their own enable control bits.

To take a measurement from the ADC, first write to the

ADC_CTRL register, Register 0x030. This register contains the

following bits:

•

Bit 0: ADC_EOC (read only). This bit is a flag for when the

ADC conversion is complete.

•

Bit 4: ST_CONV (read/write). This bit is set to start an

ADC conversion cycle.

•

Bit 5: CLK_EN (read/write). This bit enables the ADC clock.

•

Bit 6: ADC_EN (read/write). This bit enables the ADC.

•

Bit 7: ADC_CLKFREQ_SEL (read/write). This bit is used

to set the clock frequency. A low sets the clock to 2 MHz,

whereas a high sets the clock to 250 kHz.

After the ADC_CTRL register is written, it must be polled to wait

for the ADC_EOC bit to go high. When the ADC_EOC bit goes

high, the measured value can be read out from the

ADC_OUTPUT register, Register 0x031.

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