ADAR2001ACCZ-R7 datasheet(17/39 Pages) AD

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Data Sheet

ADAR2001

Rev. 0 | Page 17 of 39

STATE MACHINE SETUP

Both state machines in the ADAR2001 have configuration

registers that control various aspects of the state machine.

For the multiplier/filter sequencer, this register is

•

Bit 0 to Bit 3: MULT_STATES. Sets the number of states in

the loop (see Figure 28).

•

Bit 4: MULT_CTL_LATCH_BYP. Bypasses the latch on

the MADV and MRST pins. Setting this bit high bypasses

the latch. Regardless of the value of this bit, the new state is

preloaded on the rising edge of a MRST or MADV pulse. If

the latch is enabled, the new settings are all latched to the

appropriate section at the same time on the falling edge of

the same pulse. If the latch is bypassed, the new settings are

applied as soon as possible after the rising edge of the

pulse, with no latching and no guaranteed order.

•

Bit 5: MULT_SLP_HOLD. Prevents the multiplier/filter

block from advancing when forced into a sleep state by the

transmitter block. Used in conjunction with

MULT_SLP_CTRL. See the Sequencer Sleep Control

section for more information.

•

Bit 6: MULT_SLP_CTRL. Forces the multiplier/filter block

to sleep whenever the transmitter block is sleeping.

•

Bit 7: MULT_SEQ_EN. Enables the multiplier/filter block.

MULT_SEQ_EN must be set high for the block to operate

with the external pins.

For the transmitter sequencer, the two control registers are

•

Bit 4: TX_CTL_LATCH_BYP. Bypasses the latch on the

TxADV and TxRST pins. Setting this bit high bypasses the

latch. Regardless of the value of this bit, the new state is

preloaded on the rising edge of a TxRST or TxADV pulse.

If the latch is enabled, the new settings are all latched to

the appropriate section at the same time on the falling edge

of the same pulse. If the latch is bypassed, the new settings

are applied as soon as possible after the rising edge of the

pulse, with no latching and no guaranteed order.

•

Bit 5: TX_SLP_HOLD. Prevents the transmitter block

from advancing when forced into a sleep state by the

multiplier/filter block. Used in conjunction with

MULT_SLP_CTRL. See the Sequencer Sleep Control

section for more information.

•

Bit 6: TX_SLP_CTRL. Forces the transmitter block to sleep

whenever the multiplier/filter block is sleeping.

•

Bit 7: TX_SEQ_EN. Enables the transmitter block. Must be

set high for the block to operate with the external pins.

number of states in the loop (see Figure 28).

MULTIPLIER/FILTER STATE MACHINE

A programmable state machine provides a convenient and fast

control mechanism for the multiplier/filter block and avoids the

need for SPI writes each time the block must be reconfigured.

To enable the state machine, set the MULT_SEQ_EN bit

(Register 0x018, Bit 7) high.

Although only seven multiplier/filter modes are required for a

complete 10 GHz to 40 GHz sweep as described in Table 7, a

maximum state machine depth of 16 is provided for optimum

flexibility.

Nine preloaded modes can be assigned to any of the 16 states.

These nine modes consist of a sleep mode, a ready mode, and

the seven modes required to perform a 10 GHz to 40GHz

sweep, as shown in Table 7. It is possible to overwrite any of the

multiplier/filter modes with a custom set of operating conditions

by changing the bits in Register 0x070 to Register 0x08F.

After the modes are defined, the order in which the sequencer

moves through the desired modes must be set by filling the

state bits in Register 0x03C to Register 0x043 in order, with the

modes of interest. Any state can point to any mode, except

State 0, which always points to Mode 0. Note that the sequencer

moves through the states in order, up to the state machine

depth.

Finally, the user must define how many states are used by setting

the state machine depth (MULT_STATES, Register 0x018,

Bits[3:0]). MULT_STATES is 0 indexed. Therefore, setting the

depth to 0 leaves MULT_STATE_1 (Register 0x03C, Bits[7:4])

as the only state in the loop.

After the multiplier/filter state machine is programmed and

enabled, operation is controlled by the MRST (multiplier reset,

Pin 11) and MADV (multiplier advance, Pin 10) pins.

Alternatively, operation can be controlled through the SPI

using the MULT_RST_SPI and MULT_ADV_SPI bits

(Register 0x044, Bit 3 and Bit 2, respectively). Note that using

the SPI is slower than pulsing the sequencer pins directly.

MRST moves the pointer on the multiplier/filter state machine

to State 0 regardless of the current position of the pointer and

can be asserted at any time. State 0 always refers to Mode 0 and

cannot be set to another mode. However, Mode 0 can be

overwritten with any multiplier/filter configuration. Mode 0 is

defined in Register 0x070 and Register 0x071.

MADV pulses advance the multiplier/filter state machine

pointer one state at a time until the defined sequencer depth is

cycled through. At that point, an additional MADV pulse

moves the pointer back to State 1, which is normally set to a

ready mode (however, State 1 can be set to any mode). State 1

applies the mode defined in the MULT_STATE_1 bits

(Register 0x03C, Bits[7:4]).

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