TMS320F2810PBKA datasheet(39/173 Pages) TI

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XCLKOUT

(A)(B)

XCLKIN

(A)

C10

TMS320F2810, TMS320F2811, TMS320F2812

www.ti.com

SPRS174U – APRIL 2001 – REVISED JULY 2019

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Product Folder Links: TMS320F2810 TMS320F2811 TMS320F2812

Specifications

(1)

A load of 40 pF is assumed for these parameters.

(2)

H = 0.5tc(XCO)

(3)

The PLL must be used for maximum frequency operation.

(4)

This parameter has changed from 4096 XCLKIN cycles in the earlier revisions of the silicon.

5.12.4.2.2 Output Clock Characteristics

Table 5-9. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)(1)(2)

NO.

PARAMETER

MIN

TYP

MAX

UNIT

tc(XCO)

Cycle time, XCLKOUT

6.67(3)

tf(XCO)

Fall time, XCLKOUT

tr(XCO)

Rise time, XCLKOUT

tw(XCOL)

Pulse duration, XCLKOUT low

H – 2

H + 2

tw(XCOH)

Pulse duration, XCLKOUT high

H – 2

H + 2

PLL lock time(4)

131072tc(CI)

The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown in

Figure 5-11 is intended to illustrate the timing parameters only and may differ based on configuration.

XCLKOUT configured to reflect SYSCLKOUT.

Figure 5-11. Clock Timing

TMS320F2810PBKA 数据表(PDF) 39 Page - Texas Instruments

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