TMS320F2810PBKA datasheet(63/173 Pages) TI

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su(XD)XRD

Lead

Active

Trail

DIN

d(XCOH-XZCSL)

d(XCOH-XA)

d(XCOHL-XRDL)

d(XCOHL-XZCSH)

d(XCOHL-XRDH)

WS (Async)

XCLKOUT = XTIMCLK

XCLKOUT = 1/2 XTIMCLK

XZCS0AND1 XZCS2

XZCS6AND7

XA[0:18]

XRD

XWE

XR/W

XD[0:15]

XREADY(Asynch)

su(XRDYasynchL)XCOHL

a(A)

h(XD)XRD

h(XRDYasynchH)XZCSH

See

Notes (A)

and (B)

See Note (C)

su(XRDYasynchH)XCOHL

See Note (D)

= Don’t care. Signal can be high or low during this time.

Legend:

e(XRDYasynchH)

See Note (E)

a(XRD)

h(XRDYasynchL)

TMS320F2810, TMS320F2811, TMS320F2812

www.ti.com

SPRS174U – APRIL 2001 – REVISED JULY 2019

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Product Folder Links: TMS320F2810 TMS320F2811 TMS320F2812

Specifications

(1)

N/A = “Don’t care” for this example

All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an

alignment cycle before an access to meet this requirement.

During alignment cycles, all signals will transition to their inactive state.

During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes

alignment cycles.

For each sample, setup time from the beginning of the access can be calculated as:

D = (XRDLEAD + XRDACTIVE – 3 + n) tc(XTIM) – tsu(XRDYAsynchL)XCOHL

where n is the sample number (n = 1, 2, 3, and so forth).

Reference for the first sample is with respect to this point:

E = (XRDLEAD + XRDACTIVE – 2) tc(XTIM)

Figure 5-30. Example Read With Asynchronous XREADY Access

XTIMING register parameters used for this example:

XRDLEAD

XRDACTIVE

XRDTRAIL

USEREADY

X2TIMING

XWRLEAD

XWRACTIVE

XWRTRAIL

READYMODE

≥ 1

N/A(1)

1 = XREADY

(Async)

TMS320F2810PBKA 数据表(PDF) 63 Page - Texas Instruments

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