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PCF8536AT 数据表(PDF) 32 Page - NXP Semiconductors |
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PCF8536AT 数据表(HTML) 32 Page - NXP Semiconductors |
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32 / 54 page ![]() PCA85276 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved. Product data sheet Rev. 3 — 12 November 2018 32 of 54 NXP Semiconductors PCA85276 Automotive 40 x 4 LCD driver 11. Static characteristics [1] LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive. [2] For typical values, see Figure 23. [3] The I2C-bus interface of the PCA85276 is 5 V tolerant. [4] When tested, I2C pins SCL and SDA have no diode to VDD and may be driven to the VI limiting values given in Table 17 (see Figure 22 as well). [5] Propagation delay of driver between clock (CLK) and LCD driving signals. [6] Periodically sampled, not 100 % tested. [7] Outputs measured one at a time. Table 18. Static characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 8.0 V; Tamb = 40 C to +105 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Supplies VDD supply voltage VLCD 6.5 V 1.8 - 5.5 V VLCD > 6.5 V 2.5 - 5.5 V VLCD LCD supply voltage VDD < 2.5 V 2.5 - 6.5 V VDD 2.5 V 2.5 - 8.0 V IDD supply current fclk(ext) = 1536 Hz [1][2] -3.5 7 A VDD = 3.0 V; Tamb =25 C- 2.7 - A IDD(LCD) LCD supply current fclk(ext) = 1536 Hz [1] -23 32 A VLCD =3.0 V; Tamb =25 C -13 - A Logic[3] VIL LOW-level input voltage on pins CLK, SYNC, OSC, A0, A1, T1, SA0, SCL, SDA VSS -0.3VDD V VIH HIGH-level input voltage on pins CLK, SYNC, OSC, A0, A1, T1, SA0, SCL, SDA [4][5] 0.7VDD -VDD V IOL LOW-level output current output sink current; VOL = 0.4 V; VDD =5V on pins CLK and SYNC 1- - mA on pin SDA 3 - - mA IOH(CLK) HIGH-level output current on pin CLK output source current; VOH =4.6 V; VDD =5V 1- - mA IL leakage current VI =VDD or VSS; on pins CLK, SCL, SDA, A0, A1, T1, SA0 1- +1 A IL(OSC) leakage current on pin OSC VI =VDD 1- +1 A CI input capacitance [6] -- 7 pF LCD outputs V O output voltage variation on pins BP0 to BP3 and S0 to S39 100 - +100 mV RO output resistance VLCD = 5 V [7] on pins BP0 to BP3 - 1.5 - k on pins S0 to S39 - 6.0 - k |
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