PCF8536AT datasheet(8/54 Pages) NXP

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PCA85276

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Product data sheet

Rev. 3 — 12 November 2018

8 of 54

NXP Semiconductors

PCA85276

Automotive 40 x 4 LCD driver

An additional feature is for an arbitrary selection of LCD segments/elements to blink. This

applies to the static and 1:2 multiplex drive modes and can be implemented without any

communication overheads. With the output bank selector, the displayed RAM banks are

exchanged with alternate RAM banks at the blink frequency. This mode can also be

specified by the blink-select command.

In the 1:3 and 1:4 multiplex modes, where no alternative RAM bank is available, groups of

LCD segments/elements can blink by selectively changing the display RAM data at fixed

time intervals.

The entire display can blink at a frequency other than the nominal blink frequency. This

can be effectively performed by resetting and setting the display enable bit E at the

required rate using the mode-set command (see Table 6).

[1]

The blink frequency is proportional to the clock frequency (fclk). For the range of the clock frequency, see

Table 19.

6.2 Clock and frame frequency

6.2.1 Internal clock

The internal logic of the PCA85276 and its LCD drive signals are timed either by its

internal oscillator or by an external clock. The internal oscillator is enabled by connecting

pin OSC to pin VSS. If the internal oscillator is used, the output from pin CLK can be used

as the clock signal for several PCA85276 in the system that are connected in cascade.

6.2.2 External clock

Pin CLK is enabled as an external clock input by connecting pin OSC to VDD. The LCD

frame frequency is determined by the clock frequency (fclk).

Remark: A clock signal must always be supplied to the device; removing the clock may

freeze the LCD in a DC state, which is not suitable for the liquid crystal.

6.2.3 Timing

The PCA85276 timing controls the internal data flow of the device. This includes the

transfer of display data from the display RAM to the display segment outputs. In cascaded

applications, the correct timing relationship between each PCA85276 in the system is

maintained by the synchronization signal at pin SYNC. The timing also generates the LCD

frame frequency signal. The frame frequency signal is a fixed division of the clock

frequency from either the internal or an external clock:

Table 11.

Blink frequencies

Blink mode

Blink frequency[1]

off

blink

clk

768

----------

blink

clk

1536

-------------

blink

clk

3072

-------------

clk

-------

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