MAS3506D datasheet(9/52 Pages) MICRONAS

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PRELIMINARY DATA SHEET

MAS 3506D

Micronas

2.3. Clock Management

The complete StarMan chip set is driven by a single

crystal with a nominal frequency of 14.725 MHz.

The DRD 3515A contains the crystal oscillator and an

appropriate clock buffer to generate the clock signal

RClk. This RClk signal is used as reference clock for

the MAS 3506D by an internal clock synthesizer that

generates an internal system clock of 24.576 MHz.

This synchronized clock frequency is passed back to

the DRD 3515A for use in its embedded audio D/A

converter.

2.4. Power Supply Concept

The MAS 3506D offers an embedded controlled DC/

DC converter for battery based power supply con-

cepts. It works as an up-converter.

2.4.1. Internal Voltage Monitor

An internal voltage monitor compares the input voltage

at the VSENS pin with an internal reference value that

is adjustable via I2C bus. The PUP output pin should

be observed by the controller. It becomes inactive

when the voltage at the VSENS pin drops below the

programmed value of the reference voltage.

It is important that the WSEN must not be activated

before the PUP signal is generated. The PUP signal

thresholds are listed in Table 3–10 on page 20. The

internal voltage monitor will be activated with a high

level at Pin DCEN.

2.4.2. DC/DC Converter

The DC/DC converter of the MAS 3506D is used to

generate a fixed power supply voltage even if the chip

set is powered by battery cells in portable applications.

The DC/DC converter is designed for the application of

1 or 2 batteries or NiCd cells as shown in Fig. 2–5

which shows the standard application circuit. The DC/

DC converter is switched on by activating the DCEN

pin. Its output power is sufficient for supplying the com-

plete radio receiver.

Note: Connecting DCEN directly to VDD leads to

unexpected states of the DCCF register.

A 22

µH inductor is required for the application. The

important specification item is the inductor saturation

current rating, which should be greater than 2.5 times

the DC load current. The DC resistance of the inductor

is important for efficiency. The primary criterion for

selecting the output filter capacitor is low equivalent

series resistance (ESR), as the product of the inductor

current variation and the ESR determines the high-fre-

quency amplitude seen on the output voltage. The

Schottky diode should have a low voltage drop VD for

a high overall efficiency of the DC/DC converter. The

current rating of the diode should also be greater than

2.5 times the DC output current. The VSENS pin has

to be always connected to the output voltage.

2.4.3. Stand-by Functions

A high level at pin WSEN enables both, the DSP

including the I2C-block and the DC/DC-converter. If

the DSP-functions (audio decoding) are not needed,

the DC/DC-converter may remain active to supply

other parts of the radio. This mode is entered by set-

ting DCEN to “high” and WSEN to “low”. No I2C control

is possible in this mode.

2.4.4. Start-up Sequence

The DC/DC converter starts from a minimum input

voltage of 0.9 V. There should be no output load dur-

ing startup. WSEN must be “low”. The start-up script

should be as follows:

1. Start the DC/DC-converter with a high signal (VDD,

AVDD) at pin DCEN.

2. Wait until PUP goes “high”.

3. It is recommended to wait at least one millisecond to

guarantee that the output voltage has settled.

4. The controller may now enable the DSP with a

“high” signal at pin “WSEN”.

Please also refer to Figure 2–3.

Fig. 2–3: DC/DC operation

>0.9 V

WSEN > 2 V

DCEN

≥ 1

DSP

operation

µController

DC/DC

button

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