SN74LS175

http://onsemi.com

3

FUNCTIONAL DESCRIPTION

The LS175 consists of four edge-triggered D flip-flops

with individual D inputs and Q and Q outputs. The Clock and

Master Reset are common. The four flip-flops will store the

state of their individual D inputs on the LOW to HIGH Clock

(CP) transition, causing individual Q and Q outputs to

follow. A LOW input on the Master Reset (MR) will force

all Q outputs LOW and Q outputs HIGH independent of

Clock or Data inputs.

The LS175 is useful for general logic applications where

a common Master Reset and Clock are acceptable.

TRUTH TABLE

Inputs (t = n, MR = H)

Outputs (t = n+1) Note 1

D

Q

Q

L

L

H

H

H

L

Note 1: t = n + 1 indicates conditions after next clock.

Limits

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

Input HIGH Voltage

2.0

V

Guaranteed Input HIGH Voltage for

All Inputs

Input LOW Voltage

0.8

V

Guaranteed Input LOW Voltage for

All Inputs

Input Clamp Diode Voltage

– 0.65

– 1.5

V

Output HIGH Voltage

2.7

3.5

V

Output LOW Voltage

0.25

0.4

V

Output LOW Voltage

0.35

0.5

V

per Truth Table

I

Input HIGH Current

20

µA

Input HIGH Current

0.1

mA

Input LOW Current

– 0.4

mA

Short Circuit Current (Note 1)

–20

– 100

mA

Power Supply Current

18

mA

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.