SN74LS175

http://onsemi.com

4

Limits

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

Maximum Input Clock Frequency

30

40

MHz

Propagation Delay, MR to Output

20

20

30

30

ns

Propagation Delay, Clock to Output

13

16

25

25

ns

15 F

Limits

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

Clock or MR Pulse Width

20

ns

Data Setup Time

20

ns

Data Hold Time

5.0

ns

Recovery Time

25

ns

AC WAVEFORMS

Figure 1. Clock to Output Delays, Clock Pulse Width,

Frequency, Setup and Hold Times Data to Clock

Figure 2. Master Reset to Output Delay, Master Reset

Pulse Width, and Master Reset Recovery Time

1.3 V

1.3 V

1.3 V

Q

Q

1.3 V

*The shaded areas indicate when the input is permitted to

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

CP

CP

Q

MR

D

Q

*

1.3 V

1.3 V

DEFINITIONS OF TERMS

required for the correct logic level to be present at the logic

input prior to the clock transition from LOW to HIGH in

order to be recognized and transferred to the outputs.

following the clock transition from LOW to HIGH that the

logic level must be maintained at the input in order to ensure

continued recognition. A negative HOLD TIME indicates

that the correct logic level may be released prior to the clock

transition from LOW to HIGH and still be recognized.

required between the end of the reset pulse and the clock

transition from LOW to HIGH in order to recognize and

transfer HIGH Data to the Q outputs.