ST7LITE35 datasheet(114/167 Pages) STMICROELECTRONICS

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ST7LITE3

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LINSCI

™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d)

CONTROL REGISTER 2 (SCICR2)

Read/Write

Reset Value: 0000 0000 (00h)

Bits 7:2 Same function as in SCI mode, please re-

fer to Section 11.5.8 SCI Mode Register Descrip-

tion.

Bit 1 = RWU Receiver wake-up.

This bit determines if the SCI is in mute mode or

not. It is set and cleared by software and can be

cleared by hardware when a wake-up sequence is

recognized.

0: Receiver in active mode

1: Receiver in mute mode

Notes:

– Mute mode is recommended for detecting only

the Header and avoiding the reception of any

other characters. For more details please refer to

Section 11.5.9.3 LIN Reception.

– In LIN slave mode, when RDRF is set, the soft-

ware can not set or clear the RWU bit.

Bit 0 = SBK Send break.

This bit set is used to send break characters. It is

set and cleared by software.

0: No break character is transmitted

1: Break characters are transmitted

Note: If the SBK bit is set to “1” and then to “0”, the

transmitter will send a BREAK word at the end of

the current word.

CONTROL REGISTER 3 (SCICR3)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7= LDUM LIN Divider Update Method.

This bit is set and cleared by software and is also

cleared by hardware (when RDRF=1). It is only

used in LIN Slave mode. It determines how the LIN

Divider can be updated by software.

0: LDIV is updated as soon as LPR is written (if no

Auto Synchronization update occurs at the

same time).

1: LDIV is updated at the next received character

(when RDRF=1) after a write to the LPR register

Notes:

- If no write to LPR is performed between the set-

ting of LDUM bit and the reception of the next

character, LDIV will be updated with the old value.

- After LDUM has been set, it is possible to reset

the LDUM bit by software. In this case, LDIV can

be modified by writing into LPR / LPFR registers.

Bit 6:5 = LINE, LSLV LIN Mode Enable Bits.

These bits configure the LIN mode:

The LIN Master configuration enables:

The capability to send LIN Synch Breaks (13 low

bits) using the SBK bit in the SCICR2 register.

The LIN Slave configuration enables:

– The LIN Slave Baud Rate generator. The LIN

Divider (LDIV) is then represented by the LPR

and LPFR registers. The LPR and LPFR reg-

isters are read/write accessible at the address

of the SCIBRR register and the address of the

SCIETPR register

– Management of LIN Headers.

– LIN Synch Break detection (11-bit dominant).

– LIN Wake-Up method (see LHDM bit) instead

of the normal SCI Wake-Up method.

– Inhibition of Break transmission capability

(SBK has no effect)

– LIN Parity Checking (in conjunction with the

PCE bit)

Bit 4 = LASE LIN Auto Synch Enable.

This bit enables the Auto Synch Unit (ASU). It is

set and cleared by software. It is only usable in LIN

Slave mode.

0: Auto Synch Unit disabled

1: Auto Synch Unit enabled.

Bit 3 = LHDM LIN Header Detection Method

This bit is set and cleared by software. It is only us-

able in LIN Slave mode. It enables the Header De-

tection Method. In addition if the RWU bit in the

TIE

TCIE

RIE

ILIE

RWU

SBK

LDUM

LINE

LSLV

LASE

LHDM

LHIE LHDF

LSF

LINE

LSLV

Meaning

LIN mode disabled

LIN Master Mode

LIN Slave Mode

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