MWCT2116AFVLLPR datasheet(1/65 Pages) NXP

部件名	MWCT2116AFVLLPR

功能描述	Memory and memory interfaces

PDF	65 Pages

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制造商	NXP [NXP Semiconductors]

网页	http://www.nxp.com

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MWCT101XSF

MWCT101XS Data Sheet

Key Features

• Operating characteristics

– Voltage range: 2.7 V to 5.5 V

– Ambient temperature range: -40 °C to 105 °C for

HSRUN mode, -40 °C to 125 °C for RUN mode

• Arm™ Cortex-M4F core, 32-bit CPU

– Supports up to 112 MHz frequency (HSRUN) with

1.25 Dhrystone MIPS per MHz

– Arm Core based on the Armv7 Architecture and

Thumb®-2 ISA

– Integrated Digital Signal Processor (DSP)

– Configurable Nested Vectored Interrupt Controller

(NVIC)

– Single Precision Floating Point Unit (FPU)

• Clock interfaces

– 4 - 40 MHz fast external oscillator (SOSC)

– 48 MHz Fast Internal RC oscillator (FIRC)

– 8 MHz Slow Internal RC oscillator (SIRC)

– 128 kHz Low Power Oscillator (LPO)

– Up to 112 MHz (HSRUN) System Phased Lock

Loop (SPLL)

– Up to 50 MHz DC external square wave input clock

– Real Time Counter (RTC)

• Power management

– Low-power Arm Cortex-M4F core with excellent

energy efficiency

– Power Management Controller (PMC) with multiple

power modes: HSRUN, RUN, STOP, VLPR, and

VLPS. Note: CSEc (Security) or EEPROM writes/

erase will trigger error flags in HSRUN mode (112

MHz) because this use case is not allowed to

execute simultaneously. The device will need to

switch to RUN mode (80 Mhz) to execute CSEc

(Security) or EEPROM writes/erase.

– Clock gating and low power operation supported on

specific peripherals.

• Memory and memory interfaces

– Up to 2 MB program flash memory with ECC

– 64 KB FlexNVM for data flash memory with ECC

and EEPROM emulation. Note: CSEc (Security) or

EEPROM writes/erase will trigger error flags in

HSRUN mode (112 MHz) because this use case is

not allowed to execute simultaneously. The device

will need to switch to RUN mode (80 MHz) to

execute CSEc (Security) or EEPROM writes/erase.

– Up to 256 KB SRAM with ECC

– Up to 4 KB of FlexRAM for use as SRAM or

EEPROM emulation

– Up to 4 KB Code cache to minimize performance

impact of memory access latencies

– QuadSPI with HyperBus™ support

• Mixed-signal analog

– Up to two 12-bit Analog-to-Digital Converter

(ADC) with up to 32 channel analog inputs per

module

– One Analog Comparator (CMP) with internal 8-bit

Digital to Analog Converter (DAC)

• Debug functionality

– Serial Wire JTAG Debug Port (SWJ-DP) combines

– Debug Watchpoint and Trace (DWT)

– Instrumentation Trace Macrocell (ITM)

– Test Port Interface Unit (TPIU)

– Flash Patch and Breakpoint (FPB) Unit

• Human-machine interface (HMI)

– Up to 89 GPIO pins with interrupt functionality

– Non-Maskable Interrupt (NMI)

NXP Semiconductors

Document Number MWCT101XSF

Data Sheet: Advance Information

Rev. 3, 12/2019

This document contains information on a pre-production product. Specifications

and pre-production information herein are subject to change without notice.

类似零件编号 - MWCT2116AFVLLPR

制造商	部件名	数据表	功能描述
NXP Semiconductors	MWCT2012A	1Mb / 76P	Supports MWCT20D2AVLH, MWCT2012AVLH and MWCT20D2VLH Rev. 2.1, 05/2024
	MWCT2012AVLH	1Mb / 76P	Supports MWCT20D2AVLH, MWCT2012AVLH and MWCT20D2VLH Rev. 2, 12/2023
	MWCT20D2	1Mb / 76P	Supports MWCT20D2AVLH, MWCT2012AVLH and MWCT20D2VLH Rev. 2.1, 05/2024
	MWCT20D2A	1Mb / 76P	Supports MWCT20D2AVLH, MWCT2012AVLH and MWCT20D2VLH Rev. 2.1, 05/2024
	MWCT20D2AVLH	1Mb / 76P	Supports MWCT20D2AVLH, MWCT2012AVLH and MWCT20D2VLH Rev. 2, 12/2023

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