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CS4210 数据表(PDF) 34 Page - National Semiconductor (TI) |
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CS4210 数据表(HTML) 34 Page - National Semiconductor (TI) |
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34 / 102 page  www.national.com 34 Revision 1.0 Register Descriptions (Continued) 4.2 REGISTER SUMMARY The tables in this subsection summarize all the registers of the CS4210. Included in the tables are the register’s reset values and page references where the bit formats are found. Table 4-2. PCI Configuration Registers Summary Index Width (Bits) Access Name Reset Value Reference (Page) 00h-01h 16 R Vendor Identification Register 1000h Page 42 02h-03h 16 R Device Identification Register 000Fh Page 42 04h-05h 16 RW PCI Command Register 0000h Page 42 06h-07h 16 RW PCI Status Register 0200h Page 43 08h 8 R Device Revision ID Register 03h Page 43 09h-0Bh 24 R PCI Class Code Register 0C0010h Page 43 0Ch 8 R PCI Cache Line Size Register 00h Page 43 0Dh 8 RW PCI Latency Timer Register 50h Page 43 0Eh 8 R PCI Header Type Register 00h Page 43 0Fh 8 R PCI BIST Register 00h Page 43 10h-13h 32 RW Base Address Register 0 (BAR0): Sets base address for memory mapped OHCI Configuration Registers 00000000h Page 44 14h-17h 32 RW Base Address Register 1 (BAR1): Sets base address for memory mapped National Semiconductor device specific operational registers. 00000000h Page 44 18h-2B -- -- Reserved --- Page 44 2Ch-2Dh 16 R Subsystem Vendor Identification Register 1 Page 44 2Eh-2Fh 16 R Subsystem Identification Register 2 Page 44 30h-33h -- -- Reserved --- Page 44 34h 8 R Capabilities Pointer Register 3 Page 45 35h-3Bh -- -- Reserved --- Page 45 3Ch 8 RW Interrupt Line Register FFh Page 45 3Dh 8 R Interrupt Pin Register 01h Page 45 3Eh 8 R Min Grant Register 00h Page 45 3Fh 8 R Max Latency Register 00h Page 45 40h-43h 32 RW PCI HCI Control Register 00h Page 45 44h 8 R Capability ID Register 01h Page 45 45h 8 R Next Item Pointer Register 00h Page 45 46h-47h 16 R Power Management Capabilities Register 4 Page 46 48h-49h 16 R/W Power Management and Control Status Register 5 Page 46 4Ah 8 R Power Management CSR Bridge Support Extension Register 00h Page 47 4Bh 8 R Power Management Data Register 00h Page 47 1. The reset value must be set in the serial EEPROM to the vendor identification number assigned by the PCI SIG. 2. The reset value must be set in serial EEPROM to a unique number chosen by the user to represent this PCI device implementation. 3. The reset value is dependent upon the PCICapabilities bit in the nscControl register (BAR1+Offset 00h[20]) which can be configured by the serial EEPROM. If enabled in the EEPROM, the reset value of the register is 44h. If not enabled in the EEPROM or if no EE- PROM is present, then the reset value is 00h. 4. The reset value is dependent upon the PCICapabilities bit in the nscControl register (BAR1+Offset 00h[20]) which can be configured by serial EEPROM. If enabled in the EEPROM the reset value of this register is 4000h. If not or if no EEPROM is present, then the reset value is 000h. 5. The reset value is dependent upon the PCICapabilities bit in the nscControl register (BAR1+Offset 00h[20]) which can be configured by serial EEPROM. If enabled in the EEPROM the reset value of this register is 8000h. If not or if no EEPROM is present then the reset value is 000h. |
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