LTC4367 datasheet(13/30 Pages) AD

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LTC7000/LTC7000-1

Rev. E

For more information www.analog.com

APPLICATIONS INFORMATION

Input Stage

The LTC7000/LTC7000-1 employs CMOS compatible

input thresholds that allow a low voltage digital signal

connected to INP to drive standard power MOSFETs.

The LTC7000/LTC7000-1 contains an internal voltage

regulator which biases the input buffer connected to INP

allowing the input thresholds (VIH = 2.0V, VIL = 1.6V) to be

independent of variations in VCC. The 400mV hysteresis

between VIH and VIL eliminates false triggering due to

noise events. However, care should be taken to keep INP

from any noise pickup, especially in high frequency, high

voltage applications.

INP also contains an internal 1MΩ pull-down resistor

to ground, keeping TGDN pulled to TS during startup

and other unknown transient events. During shutdown

(VRUN<0.7V) the internal 1MΩ pull-down resistor is dis-

abled and INP becomes high impedance.

INP has an Absolute Maximum of –6V to +15V which

allows the signal driving INP to have voltage excursions

outside the normal power supply and ground range. It is

not uncommon for signals routed with long PCB traces

and driven with fast rise/fall times to inductively ring to

voltages higher than power supply or lower than ground.

Output Stage

A simplified version of the LTC7000/LTC7000-1 output

stage is shown in Figure 1. The pull-down device is an

N-channel MOSFET with a typical 1Ω RDS(ON) and the

pull-up device is a P-channel MOSFET with a typical

2.2Ω RDS(ON). The pull-up and pull-down pins have been

BST

TGUP

TGDN

VCC

INP

12V

7000 F01

–

2.2

HIGH

SPEED

150V

LEVEL

SHIFTER

CHARGE

PUMP

30µA

LTC7000/LTC7000-1

AV =1

Figure 1. Simplified Output Stage

separated to allow the turn-on transient to be controlled

while maintaining a fast turn-off.

The LTC7000/LTC7000-1 powerful output stage (1Ω pull-

down and 2.2Ω pull-up) minimizes transition losses when

driving external MOSFETs and keeps the MOSFET in the

state commanded by INP even if high voltage and high

frequency transients couple from the power MOSFET back

to the driving circuitry.

The large gate drive voltage on TGUP and TGDN reduces

conduction losses in the external MOSFET because

RDS(ON) is inversely proportional to its gate overdrive

(VGS – VTH).

SNS+ and SNS– Pins

SNS+ and SNS– are the inputs to the high side current

comparator and current monitor. The common mode

operational voltage range for these pins is 3.5V to 150V

independent of any other voltages. SNS+ also provides

power to the current comparator and current monitor

and draws approximately 21µA when not shut down and

INP is high. SNS– draws a bias current of approximately

4µA when not shut down and INP is high. When SNS+

is less than 3.2V typical (3.5V minimum), a fault condi-

tion occurs and the adjustable fault timer is enabled with

the same behavior as an overcurrent fault. Normally the

SNS pins are connected to the drain side of the external

MOSFET. However, the SNS pins can be connected to the

source side of the external MOSFET as long as the source

voltage rises above 3.5V before the Fault Timer expires.

See Fault Timer and Fault Flag section.

A filter resistor, RFLT should be placed in series with the

SNS– pin as shown in Figure 2. Note that the SNS– pin

takes 4µA of bias current which will affect the current

SNS+

SNS–

TGUP

TGDN

7000 F03

LTC7000/

LTC7000-1

INP = LO, 0µA

INP = HI, 4µA

RFLT

CFLT

RSNS

POWER

LOAD

Figure 2. Sense Pins Filtering

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