L9942 datasheet(5/37 Pages) STMICROELECTRONICS

5 / 37 page

L9942

1 Block diagram and Pin information

5/37

Table 1.

Pin Description

Symbol

Function

1, 12, 13, 24

PGND

Power ground: All pins PGND are internally connected to the heat slug.

Important: All pins of PGND must be externally connected!

3, 10, 15, 22

Power supply voltage (external reverse protection required): For EMI

reason a ceramic capacitor as close as possible to PGND is recommended.

Important: All pins of VS must be externally connected !

2, 23

QA1,QA2

Fullbridge-outputs An: The output is built by a highside and a lowside switch,

which are internally connected. The output stage of both switches is a power

DMOS transistor. Each driver has an internal reverse diode (bulk-drain-diode:

highside driver from output to VS, lowside driver from PGND to output). This

output is over-current protected.

11, 14

QB1,QB2

Fullbridge-outputs Bn: The output is built by a highside and a lowside switch,

which are internally connected. The output stage of both switches is a power

DMOS transistor. Each driver has an internal reverse diode (bulk-drain-diode:

highside driver from output to VS, lowside driver from PGND to output). This

output is over-current protected.

CLK

SPI clock input: The input requires CMOS logic levels. The CLK input has a

pull-down current. It controls the internal shift register of the SPI.

Serial data input: The input requires CMOS logic levels. The DI input has a

pull-down current. It receives serial data from the microcontroller. The data is a

16bit control word and the least significant bit (LSB, bit 0) is transferred first.

CSN

Chip Select Not input The input requires CMOS logic levels. The CSN input

has a pull-up current. The serial data transfer between device and micro

controller is enabled by pulling the input CSN to low level.

SPI data output: The diagnosis data is available via the SPI and it is a tristate-

output. The output is CMOS compatible will remain highly resistive, if the chip

is not selected by the input CSN (CSN = high)

PWM

PWM output This CMOS compatible output reflects the current duty cycle of

the internal PWM controller of bridge A. It is an high resistance output until

VCC has reached minimum voltage ore can switched off via the SPI command.

STEP

Step clock input: The input requires CMOS logic levels. The STEP input has

a pull-down current. It is clock of up and down counter of control register 0.

Rising edge starts new PWM cycle to drive motor in next position.

Charge Pump Output: A ceramic capacitor (e.g.100 nF) to VS can be

connected to this pin to buffer the charge-pump voltage.

GND

Ground: Reference potential besides power ground e.g. for reference resistor

RREF. From this pin exist a resistive path via substrate to PGND.

TEST

Test input The TEST input has a pull-down current. Pin used for production

test only. In the application it must be connected to GND.

VCC

Logic supply voltage: For this input a ceramic capacitor as close as possible

to GND is recommended.

RREF

Reference Resistor The reference resistor is used to generate a temperature

stable reference current used for current control and internal oscillator. At this

output a voltage of about 1.28V is present. The resistor should be chosen that

a current of about 200uA will flow through the resistor.

Enable input: The input requires CMOS logic levels. The EN input has a pull-

down resistor. In standby-mode outputs will be switched off and all registers

will be cleared. If EN is set to a logic high level then the device will enter the

active mode.

L9942 数据表(PDF) 5 Page - STMicroelectronics

L9942 数据表(HTML) 5 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

数据表下载