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R5F572TFFDFP 数据表(PDF) 49 Page - Renesas Technology Corp |
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R5F572TFFDFP 数据表(HTML) 49 Page - Renesas Technology Corp |
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49 / 176 page  R01DS0331EJ0100 Rev.1.00 Page 49 of 176 Feb 08, 2019 RX72T Group 2. CPU 2. CPU Figure 2.1 shows register set of the CPU. Figure 2.1 Register Set of the CPU Note 1. The stack pointer (SP) is switchable between the interrupt stack pointer (ISP) and user stack pointer (USP) by changing the value of the U bit in the PSW. R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 (SP)*1 General-purpose register b31 b0 DSP instruction register b71 b0 ACC0 (Accumulator 0) ACC1 (Accumulator 1) USP (User stack pointer) ISP (Interrupt stack pointer) INTB (Interrupt table register) PC (Program counter) PSW (Processor status word) BPC (Backup PC) BPSW (Backup PSW) FINTV (Fast interrupt vector register) FPSW (Single precision floating-point status word) Control register b31 b0 EXTB (Exception table register) |
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