6.2

Write operations on chip enable register

Write operations on chip enable register are performed independently of the state software write protect bit

(SWP) .

Following a start condition the bus master sends a device select code with the R/W bit (RW) set to 0. The device

acknowledges this, as shown in Figure 8, and waits for the address bytes where the register is located. The

device responds to each address byte with an acknowledge bit, and then waits for the data byte.

In order to write the chip enable register, address bytes must have A15 bit set to 1, all other bits A14 to A0 being

don't care.

A15 (1)

A14

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

1

X (2)

X

X

X

X

X

X

X

X

X

X

X

X

X

X

1. MSB A15 is sent first.

2. X means Don’t Care bits.

write cycle.

During the internal write cycle, serial data (SDA) is disabled internally, and the device does not respond to any

requests (NoACK).

If the three bits C2, C1 and C0 have been re-configured with a correct write command, the device will

acknowledge if the chip enable address of the device select code is equal to the new values of C2, C1 and C0,

otherwise NoACK.

Sending more than one byte will abort the write cycle (chip enable register content will not be changed).

Byte Write

Dev sel

Byte addr

Byte addr

Data in

MSv45963V1

ACK

RW

ACK

ACK

ACK

M24128X-FCU

Write operations on chip enable register

DS12680 - Rev 2

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