STM32L552CC_V01 datasheet(58/340 Pages) STMICROELECTRONICS

58 / 340 page

Functional overview

STM32L552xx

58/340

DS12737 Rev 6

The asynchronous event inputs are classified in 2 groups:

•

Configurable events (signals from I/Os or peripherals able to generate a pulse)

–

Configurable events have the following features:

Selectable active trigger edge

Interrupt pending status register bit independent for the rising and falling edge.

Individual interrupt and event generation mask, used for conditioning the CPU

wakeup, interrupt and event generation.

SW trigger possibility

•

Direct events (interrupt and wakeup sources from peripherals having an associated

flag which requiring to be cleared in the peripheral)

–

Direct events have the following features:

Fixed rising edge active trigger

No interrupt pending status register bit in the EXTI. (The interrupt pending status

flag is provided by the peripheral generating the event.)

Individual interrupt and event generation mask, used for conditioning the CPU

wakeup and event generation.

No SW trigger possibility

•

TrustZone secure events

–

The access to control and configuration bits of secure input events can be made

secure.

•

EXTI IO port selection

3.18

Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a

configurable generator with polynomial value and size.

Among other applications, the CRC-based techniques are used to verify data transmission

or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a mean to verify

the Flash memory integrity.

The CRC calculation unit helps to compute a signature of the software during runtime, which

can be ulteriorly compared with a reference signature generated at link-time and which can

be stored at a given memory location.

3.19

Flexible static memory controller (FSMC)

The flexible static memory controller (FSMC) includes two memory controllers:

•

The NOR/PSRAM memory controller

•

The NAND/memory controller

This memory controller is also named flexible memory controller (FMC).

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