STM32L412R8Y6TR datasheet(18/192 Pages) STMICROELECTRONICS

18 / 192 page

Functional overview

STM32L412xx

18/192

DS12469 Rev 8

The address of the ECC fail can be read in the ECC register.

3.5

Embedded SRAM

STM32L412xx devices feature 40 Kbyte of embedded SRAM, split into two blocks:

•

32 Kbyte mapped at address 0x2000 0000 (SRAM1)

•

8 Kbyte located at address 0x1000 0000 with hardware parity check (SRAM2).

This memory is also mapped at address 0x2000 8000, offering a contiguous address

space with the SRAM1 (8 Kbyte aliased by bit band)

This block is accessed through the ICode/DCode buses for maximum performance.

These 8 Kbyte SRAM can also be retained in Standby mode.

The SRAM2 can be write-protected with 1 Kbyte granularity.

The memory can be accessed in read/write at CPU clock speed with 0 wait states.

3.6

Firewall

The device embeds a Firewall which protects code sensitive and secure data from any

access performed by a code executed outside of the protected areas.

Each illegal access generates a reset which kills immediately the detected intrusion.

The Firewall main features are the following:

•

Three segments can be protected and defined thanks to the Firewall registers:

–

Code segment (located in Flash or SRAM1 if defined as executable protected

area)

–

Non-volatile data segment (located in Flash)

–

Volatile data segment (located in SRAM1)

•

The start address and the length of each segments are configurable:

–

Code segment: up to 1024 Kbyte with granularity of 256 bytes

–

Non-volatile data segment: up to 1024 Kbyte with granularity of 256 bytes

–

Volatile data segment: up to 128 Kbyte with a granularity of 64 bytes

•

Specific mechanism implemented to open the Firewall to get access to the protected

areas (call gate entry sequence)

•

Volatile data segment can be shared or not with the non-protected code

•

Volatile data segment can be executed or not depending on the Firewall configuration

The Flash readout protection must be set to level 2 in order to reach the expected level of

protection.

3.7

Boot modes

At startup, BOOT0 pin or nSWBOOT0 option bit, and BOOT1 option bit are used to select

one of three boot options:

•

Boot from user Flash

•

Boot from system memory

•

Boot from embedded SRAM

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