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STM32L552CEU6PTR 数据表(PDF) 272 Page - STMicroelectronics |
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STM32L552CEU6PTR 数据表(HTML) 272 Page - STMicroelectronics |
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272 / 340 page ![]() Electrical characteristics STM32L552xx 272/340 DS12737 Rev 6 tsu(MI) Data input setup time Master mode 2 - - ns tsu(SI) Slave mode 1.5 - - th(MI) Data input hold time Master mode 7.5 - - th(SI) Slave mode 3 - - ta(SO) Data output access time Slave mode 9 - 34 tdis(SO) Data output disable time Slave mode 9 - 16 tv(SO) Data output valid time Slave mode 2.7<VDD<3.6V Voltage ranges 0/1 - 9 13.75 Slave mode 1.71<VDD<3.6V Voltage ranges 0/1 -9 21.5 Slave mode 1.71<VDD<3.6V Voltage range 2 - 11.5 24.5 Slave mode(3) 1.08<VDD<1.32V -28.5 40.5 tv(MO) Master mode - 0 1 th(SO) Data output hold time Slave mode 1.71<VDD<3.6V 7.5 - - Slave mode(3) 1.08<VDD<1.32V 21 - - th(MO) Master mode 0 - - 1. Guaranteed by characterization results. 2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master having tsu(MI) = 0 while Duty(SCK) = 50%. 3. SPI mapped on GPIOG port which is supplied by VDDIO2 specified down to 1.08 V. SPI is tested in this voltage. Table 129. SPI characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max(2) Unit |
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