STM32L552CEU6PTR datasheet(279/340 Pages) STMICROELECTRONICS

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DS12737 Rev 6

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STM32L552xx

Electrical characteristics

307

Figure 54. USART slave mode timing diagram

5.3.30

FSMC characteristics

Unless otherwise specified, the parameters given in Table 132 to Table 145 for the FMC

interface are derived from tests performed under the ambient temperature, fHCLK frequency

and VDD supply voltage conditions summarized in Table 27: General operating conditions,

with the following configuration:

•

Output speed is set to OSPEEDRy[1:0] = 11

•

Capacitive load C = 30 pF

•

Measurement points are done at CMOS levels: 0.5 x VDD

Refer to Section 5.3.15: I/O port characteristics for more details on the input/output

characteristics.

Asynchronous waveforms and timings

Figure 55 through Figure 58 represent asynchronous waveforms and Table 132 through

Table 139 provide the corresponding timings. The results shown in these tables are

obtained with the following FMC configuration:

•

AddressSetupTime (ADDSET) = 0x1

•

AddressHoldTime (ADDHLD) = 0x1

•

DataHoldTime = 0x1

•

ByteLaneSetup (NBLSET) = 0x1

•

DataSetupTime (DATAST) = 0x1 (except for asynchronous NWAIT mode,

DataSetupTime = 0x5)

•

DataHoldTime (DATAHLD) = 0x1 (1THCLK for read operations and 2THCLK for write

operations)

•

BusTurnAroundDuration = 0x0

•

Capacitive load CL = 30 pF

In all timing tables, the THCLK is the HCLK clock period.

(SI)

MSB IN

BIT1 IN

LSB IN

BIT6 OUT

MSB OUT

LSB OUT

NSS input

MOSI

INPUT

MISO

OUTPUT

(SI)

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