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STM32L552CEU6PTR 数据表(PDF) 294 Page - STMicroelectronics |
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STM32L552CEU6PTR 数据表(HTML) 294 Page - STMicroelectronics |
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294 / 340 page  Electrical characteristics STM32L552xx 294/340 DS12737 Rev 6 NAND controller waveforms and timings Figure 63 through Figure 66 represent synchronous waveforms, and Table 144 and Table 145 provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration: • COM.FMC_SetupTime = 0x01 • COM.FMC_WaitSetupTime = 0x03 • COM.FMC_HoldSetupTime = 0x02 • COM.FMC_HiZSetupTime = 0x01 • ATT.FMC_SetupTime = 0x01 • ATT.FMC_WaitSetupTime = 0x03 • ATT.FMC_HoldSetupTime = 0x02 • ATT.FMC_HiZSetupTime = 0x01 • Bank = FMC_Bank_NAND • MemoryDataWidth = FMC_MemoryDataWidth_16b • ECC = FMC_ECC_Enable • ECCPageSize = FMC_ECCPageSize_512Bytes • TCLRSetupTime = 0 • TARSetupTime = 0 Table 143. Synchronous non-multiplexed PSRAM write timings(1)(2) 1. Guaranteed by characterization results, not tested in production. 2. Clock ratio R = (HCLK period /FMC_CLK period). Symbol Parameter Min Max Unit tw(CLK) FMC_CLK period R*THCLK-0.5(2) - ns td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 2.5 td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) R*THCLK/2 +1(2) - td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 2.5 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 2 - td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=0…25) - 5.5 td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=0…25) R*THCLK/2+0.5(2) - td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 2 td(CLKH-NWEH) FMC_CLK high to FMC_NWE high R*THCLK/2+1(2) - td(CLKL-Data) FMC_D[15:0] valid data after FMC_CLK low -3.5 td(CLKL-NBLL) FMC_CLK low to FMC_NBL low 1 - td(CLKH-NBLH) FMC_CLK high to FMC_NBL high R*THCLK/2+1.5(2) - tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 1.5 - th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 4 - |
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