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STM32L412R8U3PXXX 数据表(PDF) 34 Page - STMicroelectronics |
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STM32L412R8U3PXXX 数据表(HTML) 34 Page - STMicroelectronics |
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34 / 192 page  Functional overview STM32L412xx 34/192 DS12469 Rev 8 Figure 4. Clock tree MSv46900V3 PLLCLK SYSCLK MCO LSCO PLL 48 MHz clock to USB, RNG to ADCx, x=1,2 to IWDG to RTC to PWR HCLK to AHB bus, core, memory and DMA FCLK Cortex free running clock to Cortex system timer to APB1 peripherals to APB2 peripherals PCLK1 PCLK2 LSE HSI16 SYSCLK to USARTx x=2..3 to LPUART1 to I2Cx x=1,2,3 to LPTIMx x=1,2 to TIMx x=2,6,7 OSC32_OUT OSC32_IN MSI HSI16 HSE HSI16 LSI LSE HSE SYSCLK HSE MSI HSI16 MSI SYSCLK LSE OSC 32.768 kHz /32 AHB PRESC / 1,2,..512 / 8 APB1 PRESC / 1,2,4,8,16 x1 or x2 HSI16 SYSCLK LSI LSE HSI16 APB2 PRESC / 1,2,4,8,16 to TIMx x=1,15,16 x1 or x2 to USART1 LSE HSI16 SYSCLK / P / Q / R / M MSI RC 100 kHz – 48 MHz HSI RC 16 MHz HSE OSC 4-48 MHz Clock detector OSC_OUT OSC_IN / 1→16 LSI RC 32 kHz Clock source control PLL48M1CLK PLLCLK HSI RC 48 MHz HSI48 CRS MSI |
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