STPMIC1DPQR datasheet(36/140 Pages) STMICROELECTRONICS

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Refer to Section 4.2.3 LDO output voltage settings.

Dynamic voltage scaling (DVS) – When Buck voltage is changed by writing to VOUT[5:0] bits in POWER_ON

state, Buck reference is digitally stepped up/down in order to keep VOUT slew rate defined by parameter SRBK.

When a lower VOUT is requested, Buck operates in “boost reverse” mode to discharge the output capacitor with

the same slew rate SRBK, providing current back to the input supply capacitor. This improves efficiency because

energy stored in the output capacitor is not lost but “recycled” into input capacitor. For more details refer to

Figure 47. BUCKx dynamic voltage scaling (DVS) .

Bypass capability – BUCK3 and BUCK4 switch to bypass mode with 100% duty cycle when VIN voltage is below

target VOUT setting. Transition to bypass mode is fully automatic and requires no user intervention.

Overcurrent protection – When inductor current exceeds peak current limit threshold IBK1_LIM, PWM pulse is

immediately stopped, and buck starts to decrease output voltage limiting the output current. When this condition

lasts for more than tOCPDB_BUCK, BUCKx_OCP interrupt is generated.

For a detailed behavior of the device on OCP event refer to Section 5.4.7 Overcurrent protection (OCP).

VOUT Protection – BUCK4 VOUT value digital setting can be limited to 1.3 V by writing BUCK4_CLAMP bit in

Table 68. NVM_LDOS_RANK_SHR2 register.

This feature can be used to prevent destruction of low-voltage circuit connected to VOUT4, in case of erroneous/

unwanted software access to Table 38. BUCKx_MAIN_CR or Table 43. BUCKx_ALT_CR.

Start-up sequence – After the Buck is enabled, variable calibration delay is present before the output voltage

starts rising. This delay is specified as start-up delay tSU_BUCKx. For details about start-up/shutdown timings refer

to Figure 46. BUCKx start-up/shutdown timings.

Output discharge – Buck has configurable passive output discharge circuit to guarantee that shutdown time is

shorter than single ranking slot in POWER_DOWN sequence.

Discharge circuit can be configured to Slow PD (pull-down) for longer discharge time or Fast PD for faster

discharge time. Discharge duration is defined accordingly by tSD_BKx.

Slow output discharge circuit is active by default when buck is disabled.

Different behavior can be programmed in BUCKx_PD[1:0] bits of BUCKS_PD_CR register.

Figure 45. BUCKx LP to HP mode recovery time

STPMIC1

Buck converters

DS12792 - Rev 7

page 36/140

STPMIC1DPQR 数据表(PDF) 36 Page - STMicroelectronics