AM29DL164D datasheet(53/57 Pages) AMD

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DS42515

AC CHARACTERISTICS

Notes:

1. UB#s and LB#s controlled, CIOs must be high.

2. t

CW is measured from CE1#s going low to the end of write.

3. t

WR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.

4. tAS is measured from the address valid to the beginning of write.

5. A write occurs during the overlap (t

WP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when

asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A

write ends at the earliest transition when CE1#s goes high and WE# goes high. The t

WP is measured from the beginning of write

to the end of write.

Figure 32.

SRAM Write Cycle—UB#s and LB#s Control

Address

Data Valid

UB#s, LB#s

WE#

Data In

Data Out

High-Z

tWC

CE1#s

CE2s

tAW

tBW

tDW

tDH

tWR (See Note 3)

tAS

(See Note 4)

tCW

(See Note 2)

tCW (See Note 2)

tWP

(See Note 5)

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