AM29DL164D datasheet(8/57 Pages) AMD

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DS42515

PIN DESCRIPTION

A0–A17

= 18 Address Inputs (Common)

A–1, A18–A19 = 3 Address Inputs (Flash)

= Highest Order Address Input

(SRAM) Byte mode

DQ0–DQ15

= 16 Data Inputs/Outputs (Common)

CE#f

= Chip Enable (Flash)

CE#s

= Chip Enable (SRAM)

OE#

= Output Enable (Common)

WE#

= Write Enable (Common)

RY/BY#

= Ready/Busy Output

UB#s

= Upper Byte Control (SRAM)

LB#s

= Lower Byte Control (SRAM)

CIOf

= I/O Configuration (Flash)

CIOf = VIH = Word mode (x16),

CIOf = VIL = Byte mode (x8)

CIOs

= I/O Configuration (SRAM)

CIOs = VIH = Word mode (x16),

CIOs = VIL = Byte mode (x8)

RESET#

= Hardware Reset Pin, Active Low

WP#/ACC

= Hardware Write Protect/

Acceleration Pin (Flash)

VCCf

= Flash 3.0 volt-only single power sup-

ply (see Product Selector Guide for

speed options and voltage supply

tolerances)

VCCs

= SRAM Power Supply

VSS

= Device Ground (Common)

= Pin Not Connected Internally

LOGIC SYMBOL

ORDERING INFORMATION

DEVICE BUS OPERATIONS

This section describes the requirements and use of

the device bus operations, which are initiated through

the internal command register. The command register

itself does not occupy any addressable memory loca-

tion. T he r egis ter is a l a tch us ed to s t ore th e

commands, along with the address and data informa-

tion needed to execute the command. The contents of

the register serve as inputs to the internal state ma-

chine. The state machine outputs dictate the function

of the device. Tables 1 through 3 lists the device bus

operations, the inputs and control levels they require,

and the resulting output. The following subsections de-

scribe each of these operations in further detail.

16 or 8

DQ0–DQ15

A0–A17

CE#f

OE#

WE#

RESET#

UB#s

RY/BY#

WP#/ACC

A–1, A18–A19

LB#s

CIOf

CIOs

CE1#s

CE2s

Valid Combination

Order Number

Package Marking

DS42515

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