ZSC31015EAG1-R datasheet(45/53 Pages) RENESAS

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November 14, 2016

ZSC31015 Datasheet

EEPROM Restoration

If needed, the default settings for the ZSC31015 (see Table 3.5) can be reprogrammed as described in section 3.

The following sections describe EEPROM content validation and handling during and/or after system assembly.

Important: During the sawing and dicing process, there is a possibility of the EEPROM contents flipping, and

prevention cannot be guaranteed. This is primarily a concern for the factory trim settings, which are customized to

each part.

The EEPROM default values programmed during the different test levels have been selected so that customer

has the option to refresh/reprogram trim bits that might have flipped during sawing or dicing.

Important: The EEPROM lock is stored in the bit range 105:103. A value of 6HEX or 3HEX will lock the EEPROM

forever by disabling the charge pump needed for EEPROM writing. The complete contents can also be validated

using the EEPROM signature stored in bits [151:144], (see “Signature” in Table 3.5).

5.1.

Default EEPROM Contents

During the wafer level test (wafer/dice delivery) and during final test for SOP8 packaged parts, the EEPROM is

programmed with the default values listed in the Table 3.5. During the wafer level test, the Osc_trim bits [2:0] and

1V_Trim/JFET_Trim trim bits [6:3] are set to die-specific values.

5.1.1.

Osc_Trim

The oscillator frequency is trimmed to a value of 512kHz±20% using the Osc_Trim bit setting. The 3-bit setting is

copied twice to Cust_ID1[134:132] and [130:128] and then a third time to Cust_ID2[138:136] to ensure the factory

settings are retained so that the customer can reprogram these values in the Osc_Trim bit if needed. Based on

the most probable trimming, the default values for the Osc_Trim bits are always set to 0HEX during factory testing

to guarantee communication even if bits have flipped.

5.1.2.

1V_Trim/JFET_Trim

The 5V reference for the JFET regulation is factory trimmed during the final test to 5V±15mV using the 1V_Trim/

JFET_Trim bit setting. The 4-bit setting stored in EEPROM bits [6:3] is copied twice to the Cust_ID0 bits [127:124]

and [123:120] to ensure the factory settings are retained so that the customer can reprogram these values in the

1V_Trim/JFET_Trim bits if needed.

5.2.

EEPROM Restoration Procedure

After module assembly, the EEPROM content should be refreshed. If JFET regulation is not used for the user

’s

application and optimized response time is not an important criterion, write the default values shown in Table 3.5

to the EEPROM bit range [143:7] and retain the existing values in the bit range [6:0]. If JFET regulation or

optimized response time is required, the bit restoration procedure shown in the flow chart in Figure 5.1 must be

used to keep the factory settings programmed during the testing. If customer oscillator trimming is required, see

ZSC31015_Tech_Notes_JFET_and_Osc_Trimming_revX.X .pdf for instructions.)

Note: The EEPROM signature is re-calculated and updated after every EEPROM writing.

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