ZSC31015EIG1-R datasheet(42/53 Pages) RENESAS

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November 14, 2016

ZSC31015 Datasheet

ZSC31015

Bsink

VBP

ExtTemp

VBN

VSS

Sig

VDD

Vgate

0.1

F

Vsupply

Ground

+2.7 to +5.5 V

OUT

Optional Bsink

Application Circuit Examples

The minimum output analog load resistor is RL= 5k. This optional load resistor can be configured as a pull-up or

pull-down. If it is configured as a pull-down, it cannot be part of the module to be calibrated because this would

prevent proper operation of the ZACwire

TM. If a pull-down load is desired, it must be added to system after module

calibration.

There is no output load capacitance needed.

EEPROM contents: OUTPUT_select, Config_JFET_Regulation, 1V_Trim/JFET-Trim.

4.1.

Three-Wire Rail-to-Rail Ratiometric Output

This example shows an application circuit for rail-to-rail ratiometric voltage output configuration with temperature

compensation via an external diode. The same circuitry is applicable for a 0 to 1V absolute analog output.

Figure 4.1

Rail-to-Rail Ratiometric Voltage Output

– Temperature Compensation via External Diode

The optional bridge sink allows a power savings of bridge current. The output voltage can be either



Rail-to-rail ratiometric analog output VDD(=Vsupply).



0 to 1V absolute analog output. The absolute voltage output reference is trimmable 1V (+/-3mV) in the

1V Output Mode via a 4-bit EEPROM field. See section 2.4.3).

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