Generally, unity gain configuration is the worst situation for stability and the ability to drive large capacitive loads.

For additional capacitive load drive capability in unity-gain configuration, stability can be improved by inserting a

ringing while maintaining DC performance for purely capacitive loads. However, if there is a resistive load in

parallel with the capacitive load, a voltage divider is created introducing a gain error at the output and slightly

capacitive load acceptable from a stability point-of-view as described in the figure below:

5.8

Resistor values for high speed op-amp design

Due to its high gain bandwidth product (GBP), this op-amp is particularly sensitive to parasitic impedances. Board

parasitics should be taken into account in any sensitive design. Indeed, excessive parasitics (both capacitive

and inductive) in the op-amp frequency range can alter performances and stability. These issues can often be

mitigated by lowering the resistive impedances.

of both the op-amp (as documented in Table 5 to Table 7 and illustrated in Figure 46) and the PCB can generate

a pole below or in the same order of magnitude than the closed-loop bandwidth of the circuit. In this case, the

feedback circuit is not able to fully play its role at high frequency, and the application can be unstable. This issue

can happen when the schematic gain is low (typically < 5), or the device is used in follower mode with a resistor in

TSV791, TSV792

Resistor values for high speed op-amp design

DS13480 - Rev 1

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