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F2270 Datasheet

January 16, 2019

Application Information

The F2270 has been optimized for use in high performance RF applications from 5MHz to 1800MHz and has a full operating range of 5MHz to

3000MHz.

Default Start-up

VMODE should be tied to either logic LOW (ground) or logic HIGH. If the VCTRL pin is left floating, the part will power up in the minimum attenuation

state when VMODE = LOW or in the maximum attenuation state when VMODE = HIGH.

VMODE

The VMODE pin is used to set the slope of the attenuation. The attenuation is varied by VCTRL as described in the next section. Setting VMODE to

a logic LOW (HIGH) will set the attenuation slope to negative (positive). A negative (positive) slope is defined as an increased (decreased)

attenuation with increasing VCTRL voltage. The Evaluation Kit provides has an on-board jumper to manually set VMODE. Install a jumper on header

J7 from VMODE to the pin marked Lo (Hi) to set the device for a negative (positive) slope (see Figure 58).

VCTRL

The voltage level on the VCTRL pin is used to control the attenuation of the F2270. At VCTRL =0V, the attenuation is a minimum (maximum) in the

negative (positive) slope mode. An increasing voltage on VCTRL produces an increasing (decreasing) attenuation respectively. The VCTRL pin

has an on-chip pull-up ESD diode so VDD should be applied before VCTRL is applied (see “Recommended Operating Conditions” for details). If

this sequencing is not possible, then resistor R5 in the application circuit (see Figure 60) should be set to 1kΩ to limit the current into the VCTRL

pin.

RF1 and RF2 Ports

The F2270 is a bi-directional device, allowing RF1 or RF2 to be used as the RF input. RF1 has some enhanced linearity performance, and

therefore should be used as the RF input, when possible, for best results. The F2270 has been designed to accept high RF input power levels;

therefore, VDD must be applied prior to the application of RF power to ensure reliability. DC blocking capacitors are required on the RF pins and

should be set to a value that results in a low reactance over the frequency range of interest. External series inductors can be added on the RF1

and RF2 lines close to the device to improve the higher frequency match.

Power Supplies

The VDD supply pin should be bypassed with external capacitors to minimize noise and fast transients. Supply noise can degrade performance,

and fast transients can trigger ESD clamps and cause them to fail. Supply voltage changes or transients should have a slew rate smaller than

1V/20µs. In addition, all control pins should remain at 0V (+/- 0.3V) while the supply voltage ramps or while it returns to zero.

Control Pin Interface

If control signal integrity is a concern and clean signals cannot be guaranteed due to overshoot, undershoot, or ringing, etc., then implementing

the circuit shown in Figure 57 at the input of each control pin is recommended. This applies to control pins 14 (VCTRL) and 16 (VMODE) as

shown in Figure 57. Note the recommended resistor and capacitor values do not necessarily match the Evaluation Kit BOM for the case of poor

control signal integrity.

Extended Bandwidth Tuning (EBT)

There are cases where the return loss for the RF ports needs to be better than 18 dB across the frequency range. For this case, adding series

inductors just next to the package on the RF ports will accomplish this. The addition of these inductors, 2.4nH on RF1 and 2.8nH on RF2, will

degrade the insertion loss and return loss at frequencies above 2GHz.

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