MITSUBISHI < STD. LINEAR ICs >

M62320P,FP

2/20,1998(rev) (

/ 9 )

MITSUBISHI ELECTRIC

8-BIT I/O EXPANDER for I C BUS

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FUNCTIONAL BLOCKS

I C BUS interface

The I C BUS interface recognizes start/stop conditions, a slave address and a write/read mode selection

by receiving SDA,SCL,CS0,CS1 and CS2 signals and then the latch pulses, dedicated to each data latch

are generated.

Data Latch

This IC has 3 types of data latch : the I/O setting data latch, the input data latch and the output data latch

and each latch is controlled by the I C BUS interface.

• I/O setting data latch

byte after receiving the slave address byte in the write mode from the master. In case this latch is set to

high, the data is transferred from the I C BUS interface to the parallel data terminals. In the opposite

transmission : from the parallel data terminals to the I C BUS, it is set to low.

• Output data latch

In the write mode, the data from the I C BUS to the parallel data terminals is latched. When the master

transmits output data after a setting in write mode, the output data is taken into the latches.

• Input data latch

In the read mode, the data of parallel data terminals is latched in the input data latches. The input data is

taken into the latches from the parallel data terminals on every 8th negative edge of SCL clock . The

latched data is output to the master through the sift resistor. On the output terminal assigned by the I /

O setting latch, the input data latch takes the state of the output terminal.

Parallel input / output port

In case I/O setting latch is set to low (the input mode), each parallel terminal becomes hi-impedance and

is able to accept a input. In another case I/O setting latch is set to high (output mode), each parallel

terminal outputs a data according to the state of the output data latch.

Power on reset

When power is turned on, each latch is reset and then the parallel data I/O terminals become

hi-impedance (input mode).

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