LTC7103 datasheet(13/48 Pages) AD

13 / 48 page

LTC7871

Rev. 0

For more information www.analog.com

OPERATION

Main Control Loop

The LTC7871 is a bidirectional, constant-frequency, cur-

rent mode buck or boost switching regulator controller

with six channels operating equally out of phase. The

LTC7871 is capable of delivering power from VHIGH to

VLOW as well as from VLOW back to VHIGH. When power

is delivered from VHIGH to VLOW, the LTC7871 operates

as a peak-current mode constant-frequency buck regula-

tor; and when power delivery is reversed, it operates as a

valley current mode constant-frequency boost regulator.

Four control loops, two for current and two for voltage,

allow control of voltage or bidirectional current on either

VHIGH or VLOW. The LTC7871 uses an ADI proprietary cur-

rent sensing, current mode architecture. During normal

buck mode operation, the top MOSFET is turned on every

cycle when the oscillator sets the RS latch, and turned off

when the main current comparator, ICMP, resets the RS

latch. The peak inductor current at which ICMP resets the

RS latch is controlled by the voltage on the ITH pin, which

is the output of the error amplifier, EA. The error amplifier

receives the feedback signal and compares it to the inter-

nal 1.2V reference. When the load current increases, it

causes a slight change in the feedback pin voltage relative

to the 1.2V reference, which in turn causes the ITH voltage

to change until the inductor’s average current equals the

new load current. After the top MOSFET has turned off,

the bottom synchronous MOSFET is turned on until the

beginning of the next cycle.

In either buck or boost mode, the two current control

loops always monitor the maximum average inductor cur-

rent. When it increases above the thresholds, the current

loops will take over the ITH pin control from the voltage

loop. As a result, the maximum average inductor current

is limited.

The main control loop is shut down by pulling the RUN pin

low. Releasing the RUN pin allows an internal 2μA current

source to pull it up. When the RUN pin reaches 1.22V,

the IC is powered up and the pull-up current increases to

6μA. When the RUN pin is low, all functions are kept in a

controlled shutdown state.

Current Sensing with Low DCR or RSENSE

The LTC7871 employs a unique architecture to enhance

the signal-to-noise ratio with low current sense offsets.

This enables it to operate with a small current sense signal

from a very low value inductor DCR to improve power

efficiency, and reduce jitter due to switching noise which

could corrupt the signal. Each channel has two positive

current sense pins, SNSD+ and SNSA+, which share

the negative current sense pin SNS–. These sense pins

acquire signals and process them internally to provide

the response equivalent to a DCR sense signal that has

a 14dB (5 times) signal-to-noise ratio. Accordingly, the

current limit threshold is still a function of the inductor

peak-current and its DCR value and can be accurately set

from 10mV to 50mV in 10mV steps with the ILIM pin.

DRVCC/EXTVCC/V5 Power

Power for the external top and bottom MOSFET drivers

is derived from the DRVCC pin. The DRVCC voltage can

be set to 5V, 8V, or 10V using the DRVSET pin. When

the EXTVCC pin is left open or tied to a voltage less than

the switchover voltage programmed by the DRVSET pin,

an internal linear regulator supplies DRVCC power from

VHIGH. When EXTVCC is taken above the switchover volt-

age, the internal regulator between VHIGH and DRVCC is

turned off, and a second internal regulator is turned on

between EXTVCC and DRVCC. Each top MOSFET driver is

biased from a floating bootstrap capacitor, which nor-

mally recharges during each off cycle through an external

diode when the top MOSFET turns off. If the input volt-

age, VHIGH, decreases to a voltage close to VLOW, the

loop may enter dropout and attempt to turn on the top

MOSFET continuously. The dropout detector detects this

and forces the top MOSFET off for about one-twelfth of

the clock period plus 160ns every fifth cycle to allow the

bootstrap capacitor to recharge.

Most of the internal circuitry is powered from the V5

rail that is generated by an internal linear regulator from

DRVCC. The V5 pin needs to be bypassed with a minimum

4.7μF external capacitor to SGND. This pin provides a 5V

output that can supply up to 20mA of current. See the

Applications Information section for more details.

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