LTC7103 datasheet(24/48 Pages) AD

24 / 48 page

LTC7871

Rev. 0

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An optional Schottky diode across the bottom MOSFET

conducts during the dead time between the conduction

of the two large power MOSFETs in buck mode. This pre-

vents the body diode of the bottom MOSFET from turning

on, storing charge during the dead time and requiring

a reverse-recovery period which could cost as much as

several percent in efficiency. A 2A to 8A Schottky is gen-

erally a good compromise for both regions of operation

due to the relatively small average current. Larger diodes

result in additional transition loss due to their larger

junction capacitance.

CHIGH and MOSFETs Selection (on VHIGH and VLOW)

In continuous mode, the source current of the top

MOSFET is a square wave of duty cycle (VLOW)/(VHIGH).

To prevent large voltage transients, a low ESR capaci-

tor sized for the maximum RMS current of one channel

must be used. In the following discussion, it is assumed

that CIN is CHIGH, COUT is CLOW, VIN is VHIGH, and VOUT is

VLOW. The maximum RMS capacitor current is given by:

CIN Required IRMS ≈

IMAX

VIN

VOUT

(

) VIN–VOUT

(

)

⎡⎣

⎤⎦

1/2

This formula has a maximum at VIN = 2VOUT, where

IRMS = IOUT/2. This simple worst-case condition is com-

monly used for design because even significant deviations

do not offer much relief. Note that capacitor manufacturers’

ripple current ratings are often based on only 2000 hours

of use.

This makes it advisable to further derate the capacitor, or

to choose a capacitor rated at a higher temperature than

required. Several capacitors may be paralleled to meet size

or height requirements in the design. Ceramic capacitors

can also be used for CIN. Always consult the manufacturer

if there is any question.

Ceramic capacitors are becoming very popular for small

designs but several cautions should be observed. X7R, X5R

and Y5V are examples of a few of the ceramic materials

used as the dielectric layer, and these different dielectrics

have very different effect on the capacitance value due to

the voltage and temperature conditions applied. Physically,

if the capacitance value changes due to applied voltage

change, there is a concomitant piezo effect which results

the controller is operating in continuous mode the duty

cycles for the top and bottom MOSFETs are given by:

Top SwitchDuty Cycle =

VLOW

VHIGH

Bottom SwitchDuty Cycle =

VHIGH – VLOW

VHIGH

⎛

⎝

⎜

⎞

⎠

⎟

The power dissipation for the top and bottom MOSFETs

at maximum output current are given by:

PTOP =

VLOW

VHIGH

IMAX

( )2 1+δ

( )RDS(ON)+t

VHIGH

(

IMAX

⎛

⎝⎜

⎞

⎠⎟

RDR

( ) CMILLER

(

)•

DRVCC – VTH(MIN)

VTH(MIN)

⎡

⎣

⎢

⎤

⎦

⎥

• f

PBOT =

VHIGH – VLOW

VHIGH

IMAX

( )2 1+δ

( )RDS(ON)

IMAX = Maximum Inductor Current.

where

δ is the temperature dependency of RDS(ON), RDR

is the effective top driver resistance; VHIGH is the drain

potential and the change in drain potential in the particular

application. VTH(MIN) is the data sheet specified typical

gate threshold voltage specified in the power MOSFET

data sheet at the specified drain current. CMILLER is the

calculated capacitance using the gate charge curve from

the MOSFET data sheet and the technique described

above.

Both MOSFETs have I2R losses while the topside

N-channel equation includes an additional term for tran-

sition losses, which peak at the highest input voltage.

The bottom MOSFET losses are greatest at high VHIGH

voltage when the top switch duty factor is low or during

a VLOW short-circuit when the bottom switch is on close

to 100% of the period.

The term (1 +

δ) is generally given for a MOSFET in the

form of a normalized RDS(ON) vs temperature curve, but

δ = 0.005/°C can be used as an approximation for low

voltage MOSFETs.

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