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ADRF5515BCPZN-R7 数据表(PDF) 1 Page - Analog Devices

部件名 ADRF5515BCPZN-R7
功能描述  Dual-Channel, 3.3 GHz to 4.0 GHz, 20 W Receiver Front End
PDF  15 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADRF5515BCPZN-R7 数据表(HTML) 1 Page - Analog Devices

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Dual-Channel, 3.3 GHz to 4.0 GHz,
20 W Receiver Front End
Data Sheet
ADRF5515
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother
rights of third parties that may result from its use. Specifications subject to change without notice.
No license is granted by implication or otherwise under any patent or patent rights of Analog
Devices.Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2020 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
FEATURES
Integrated dual-channel RF front end
2-stage LNA and high power silicon SPDT switch
On-chip bias and matching
Single-supply operation
Gain
High gain mode: 33 dB typical at 3.6 GHz
Low gain mode: 16 dB typical at 3.6 GHz
Low noise figure
High gain mode: 1.0 dB typical at 3.6 GHz
Low gain mode: 1.0 dB typical at 3.6 GHz
High isolation
RXOUT-CHA and RXOUT-CHB: 45 dB typical
TERM-CHA and TERM-CHB: 60 dB typical
Low insertion loss: 0.45 dB typical at 3.6 GHz
High power handling at TCASE = 105°C
Full lifetime
LTE average power (9 dB PAR): 43 dBm
High OIP3 (high gain mode): 32 dBm typical
Power-down mode and low gain mode for LNA
Low supply current
High gain mode: 86 mA typical at 5 V
Low gain mode: 36 mA typical at 5 V
Power-down mode: 12 mA typical at 5 V
Positive logic control
6 mm × 6 mm, 40-lead LFCSP
Pin compatible with the ADRF5545A, 10 W version
APPLICATIONS
Wireless infrastructure
TDD massive multiple input and multiple output and active
antenna systems
TDD-based communication systems
GENERAL DESCRIPTION
The ADRF5515 is a dual-channel, integrated RF, front-end,
multichip module designed for time division duplexing (TDD)
applications. The device operates from 3.3 GHz to 4.0 GHz.
The ADRF5515 is configured in dual channels with a cascading,
two-stage, LNA and a high power silicon SPDT switch.
In high gain mode, the cascaded two-stage LNA and switch
offer a low noise figure of 1.0 dB and a high gain of 33 dB at
3.6 GHz with an output third-order intercept point (OIP3) of
32 dBm (typical). In low gain mode, one stage of the two-stage
LNA is in bypass, providing 16 dB of gain at a lower current of
36 mA. In power-down mode, the LNAs are turned off and the
device draws 12 mA.
FUNCTIONAL BLOCK DIAGRAM
1
GND
2
GND
3
ANT-CHA
4
GND
5
SWCTRL-CHAB
6
SWVDD-CHAB
7
GND
8
ANT-CHB
9
GND
10
GND
23 GND
24 BP-CHB
25 NIC
26 PD-CHAB
27 BP-CHA
28 GND
29 RXOUT-CHA
30 GND
22 RXOUT-CHB
21 GND
ADRF5515
Figure 1.
In transmit operation, when RF inputs are connected to a
termination pin (TERM-CHA or TERM-CHB), the switch
provides low insertion loss of 0.45 dB and handles long-term
evolution (LTE) average power (9 dB peak to average ratio
(PAR)) of 43 dBm for full lifetime operation.
The ADRF5515 is pin-compatible with the ADRF5545A, 10 W
version, which operates from 2.4 GHz to 4.2 GHz.
The ADRF5515 does not require any matching components at
the RF ports that are internally matched to 50 Ω. The ANT and
TERM ports are also internally ac-coupled. Therefore, only
receiver ports require external dc blocking capacitors.
The device comes in an RoHS compliant, compact, 6 mm ×
6 mm, 40-lead LFCSP.


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