TMS320F28375DPZP datasheet(92/226 Pages) TI

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8.9.9.3.2 Synchronous RAM

Section 8.9.9.3.2.1 shows the EMIF synchronous memory timing requirements. Section 8.9.9.3.2.2 shows the

EMIF synchronous memory switching characteristics. Figure 8-25 and Figure 8-26 show the synchronous

memory timing diagrams.

8.9.9.3.2.1 EMIF Synchronous Memory Timing Requirements

NO.

MIN

MAX

UNIT

tsu(EMIFDV-EM_CLKH)

Input setup time, read data valid on EMxD[y:0] before EMxCLK rising

th(CLKH-DIV)

Input hold time, read data valid on EMxD[y:0] after EMxCLK rising

1.5

8.9.9.3.2.2 EMIF Synchronous Memory Switching Characteristics

NO.

PARAMETER

MIN

MAX

UNIT

tc(CLK)

Cycle time, EMIF clock EMxCLK

tw(CLK)

Pulse width, EMIF clock EMxCLK high or low

td(CLKH-CSV)

Delay time, EMxCLK rising to EMxCS[y:2] valid

toh(CLKH-CSIV)

Output hold time, EMxCLK rising to EMxCS[y:2] invalid

td(CLKH-DQMV)

Delay time, EMxCLK rising to EMxDQM[y:0] valid

toh(CLKH-DQMIV)

Output hold time, EMxCLK rising to EMxDQM[y:0] invalid

td(CLKH-AV)

Delay time, EMxCLK rising to EMxA[y:0] and EMxBA[y:0] valid

toh(CLKH-AIV)

Output hold time, EMxCLK rising to EMxA[y:0] and EMxBA[y:0] invalid

td(CLKH-DV)

Delay time, EMxCLK rising to EMxD[y:0] valid

toh(CLKH-DIV)

Output hold time, EMxCLK rising to EMxD[y:0] invalid

td(CLKH-RASV)

Delay time, EMxCLK rising to EMxRAS valid

toh(CLKH-RASIV)

Output hold time, EMxCLK rising to EMxRAS invalid

td(CLKH-CASV)

Delay time, EMxCLK rising to EMxCAS valid

toh(CLKH-CASIV)

Output hold time, EMxCLK rising to EMxCAS invalid

td(CLKH-WEV)

Delay time, EMxCLK rising to EMxWE valid

toh(CLKH-WEIV)

Output hold time, EMxCLK rising to EMxWE invalid

td(CLKH-DHZ)

Delay time, EMxCLK rising to EMxD[y:0] tri-stated

toh(CLKH-DLZ)

Output hold time, EMxCLK rising to EMxD[y:0] driving

TMS320F28379D, TMS320F28379D-Q1, TMS320F28378D, TMS320F28377D

TMS320F28377D-Q1, TMS320F28376D, TMS320F28375D, TMS320F28374D

SPRS880O – DECEMBER 2013 – REVISED FEBRUARY 2021

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