LT8253EUFDM datasheet(12/20 Pages) AD

12 / 20 page

LT8253/LT8253A

Rev. 0

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APPLICATIONS INFORMATION

for LT8253A. Selection of the switching frequency is a

tradeoff between efficiency and component size. Low

frequency operation improves efficiency by reducing

MOSFET switching losses, but requires larger inductor

and capacitor values. For high power applications, con-

sider operating at lower frequencies to minimize MOSFET

heating from switching losses. For low power applica-

tions, consider operating at higher frequencies to mini-

mize the total solution size.

In addition, the specific application also plays an impor-

tant role in switching frequency selection. In a noise-sen-

sitive system, the switching frequency is usually selected

to keep the switching noise out of a sensitive frequency

band.

Switching Frequency Setting

The switching frequency of the LT8253/LT8253A can be

set by the internal oscillator. With the SYNC/SPRD pin

pulled to ground, the switching frequency is set by a resis-

tor from the RT pin to ground. Table 1 and Table 2 show

RT resistor values of common switching frequencies for

LT8253 and LT8253A, respectively.

Table 1. LT8253 Switching Frequency vs RT Value (1% Resistor)

fOSC (kHz)

RT (k)

150

309

200

226

300

140

400

100

500

600

650

51.1

Table 2. LT8253A Switching Frequency vs RT Value (1%

Resistor)

fOSC (MHz)

RT (k)

0.6

267

0.8

191

1.0

147

1.2

118

1.4

97.6

1.6

82.5

1.8

66.5

2.0

59.0

Spread Spectrum Frequency Modulation

Switching regulators can be particularly troublesome for

applications where electromagnetic interference (EMI) is

a concern. To improve the EMI performance, the LT8253/

LT8253A implement a triangle spread spectrum frequency

modulation scheme. With the SYNC/SPRD pin tied to

INTVCC, the LT8253 spreads its switching frequency

±15% around and the LT8253A spreads its switching

frequency 25% above the internal oscillator frequency.

Frequency Synchronization

The LT8253/LT8253A switching frequency can be syn-

chronized to an external clock using the SYNC/SPRD pin.

Driving the SYNC/SPRD with a 50% duty cycle waveform

is always a good choice, otherwise maintain the duty cycle

between 10% and 90%.

Inductor Selection

The switching frequency and inductor selection are inter-

related in that higher switching frequencies allow the use

of smaller inductor and capacitor values. The inductor

value has a direct effect on ripple current. The highest cur-

rent ripple ∆IL% happens in the buck region at VIN(MAX),

and the lowest current ripple ∆IL% happens in the boost

region at VIN(MIN). For any given ripple allowance set by

customers, the minimum inductance can be calculated as:

LBUCK >

VOUT • VIN(MAX) � VOUT

(

)

f • IOUT(MAX) • � IL% • VIN(MAX)

LBOOST >

VIN(MIN)

2 • V

OUT � VIN(MIN)

(

)

f • IOUT(MAX) • � IL% • VOUT

where:

� IL% =

� IL

IL(AVG)

f is switching frequency

VIN(MIN) is minimum input voltage

VIN(MAX) is maximum input voltage

VOUT is output voltage

IOUT(MAX) is maximum output current

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